Insulated-gate field-effect thin film transistors

• US 7,265,421 B2
• Filed: 11/02/2004
• Issued: 09/04/2007
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Viciciv Technology, Inc.
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Tran; Minhloan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US10/979,024
• Publication Number:
  US 20050121721A1
• Time in Patent Office: 1,036 Days
• Field of Search: 257/347, 257/348, 257/350, 257/351, 257/407, 257/402, 257/353, 257/403, 257/404, 257/412, 257/66, 257/57, 438/300
• US Class Current: 257/348
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A new Insulated-Gate Field-Effect Thin Film Transistor (Gated-FET) is disclosed. A semiconductor thin film Gated-FET device, comprising: a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer, said gate region receiving a gate voltage comprised of: a first level that modulate said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said thin film layer in the channel region; and a second level that modulate said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate surface of the thin film layer in said channel region.

Claims

1. A semiconductor thin film Gated-FET device, comprising:

a semiconductor thin film layer positioned on a first insulator, said first insulator adequately thick to minimize or eliminate any influence of voltages from below; and

a channel region formed in a fairly uniformly doped portion of said semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and

a gate terminal coupled to a single gate region formed above said channel region, said gate region formed on a gate material deposited over a gate insulator layer, said gate insulator layer further deposited over the semiconductor thin film layer;

wherein;

a first voltage level at the gate fully depletes all of the majority carriers from the entire thin film layer in said channel region to create a non-conductive channel; and

a second voltage level at the gate accumulates the majority carriers near the gate surface of the thin film layer in said channel region to create a conductive channel.

2. The device in claim-1 further comprised of:

a source region and a drain region formed in fairly heavily doped portions of the semiconductor thin film layer, wherein said channel region is formed in between the source and drain regions; and

a source terminal is coupled to said source region, a drain terminal is coupled to said drain region, and said source and drain regions have a higher level of the same dopant type as said channel region.

3. The device of claim-1, wherein the channel comprises one of a single crystal, polycrystalline Silicon, a re-crystallized Silicon, and any other semiconductor material.

4. The device of claim-1, wherein the gate comprises one of a conductor, a refractory metal, a heavily doped poly-Silicon and a doped semiconductor material.

5. The device of claim-1, wherein the first insulator comprises one of an oxide, an oxy-nitride, a nitride and a dielectric material.

6. The device of claim-1, wherein the gate insulator comprises one of an oxide, an oxy-nitride, a nitride and a dielectric material.

7. The device in claim-2 further comprised of an off state with said gate terminal below a threshold voltage level;

wherein said thin film channel substantially not conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage.

8. The device in claim-2 further comprised of an on state with said gate terminal above a threshold voltage level;

wherein said thin film channel conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage.

9. The device in claim-2 further comprised of an on state with said gate terminal above a flat band voltage level;

wherein said thin film channel substantially conducting a current between said drain and source regions for a differential bias voltage ranging from zero to a system power supply voltage, and said conducting current enhanced by an accumulation of majority carriers above said channel doping level near the gate insulator surface.

10. The device in claim-2 further comprised of a Gated-NFET device comprising said source, channel and drain regions doped with an N type dopant;

wherein said gate material having a positive flat band voltage, and said source region connected to a lower voltage compared to said drain region.

11. The device in claim-10 further comprises of:

an off state defined by said gate to said source voltage difference in a range from a system ground voltage V_S to a first threshold voltage V_TN; and

an on state defined by said gate to said source voltage difference in a range from said first threshold voltage V_TN to a system power supply voltage V_D.

12. The device in claim-10 further comprising a P+ doped poly-Silicon gate material;

wherein said source and drain regions defined by lightly doped N type tip regions adjacent to said channel region self aligned to said gate edge, and said source and drain regions outside of said lightly doped tip regions fully salicided and self aligned to said tip regions.

13. The device in claim-2 further comprised of a Gated-PEET device comprising said source, channel and drain regions doped with a P type dopant;

wherein said gate material having a negative flat band voltage, and said source region connected to a higher voltage compared to said drain region.

14. The device in claim-13 further comprises of:

an off state defined by said gate to said source voltage difference in a range from a system ground voltage V_S to a first threshold voltage V_TP; and

an on state defined by said gate to said source voltage difference in a range from said first threshold, voltage V_TP to a system power supply voltage V_D.

15. The device in claim-13 further comprising an N+ doped poly-Silicon gate material;

wherein said source and drain regions defined by lightly doped P type tip regions adjacent to said channel region self aligned to said gate edge, and said source and drain regions outside of said lightly doped tip regions fully salicided and self aligned to said tip regions.

16. A three terminal semiconductor thin film Gated-FET device, comprising:

a semiconductor thin film layer positioned on an insulator, said insulator adequately thick to minimize or eliminate any influence of electrodes from below the insulator; and

a source terminal coupled to a source region and a drain terminal coupled to a drain region, said source and drain regions heavily doped with a first dopant type, a uniformly doped channel region positioned in between said source and drain regions comprising a lower doping level of the first dopant type, said source, drain and channel regions formed in the thin film layer, said channel thickness comprising the entire thin film thickness; and

a gate terminal coupled to a gate region, said gate region formed above the channel region on a gate material deposited over a gate insulator layer deposited on the thin film layer, wherein;

a first voltage level at the gate terminal fully depletes all of the majority carriers from the entire thin film layer in said channel region to create a non-conductive channel; and

a second voltage level at the gate terminal accumulates majority carriers near the gate surface of the thin film layer in said channel region to create a conductive channel.

17. The device of claim-16, wherein said non-conductive channel resistance is in a range approximately 10 KOhm to 1 TOhm, and preferably in the range 100 KOhm to 1 TOhm, and more preferably in the range 1 MOhm to 1 TOhms.

18. The device of claim 16, wherein the ratio of said device conductive channel current to said device non-conductive channel current is in a range approximately 100 to 10,000,000,000, and preferably in a range 1000 to 10,000,000,000, and more preferably in a range 10,000 to 10,000,000,000.

19. The device as in claim 16, wherein the semiconductor thin film layer thickness is in the range 30 to 600 Angstroms, and preferably in the range 100 to 400 Angstroms and more preferably in the range 200 to 350 Angstroms.

20. A semiconductor thin film Gated-FET device, comprising:

a lightly doped resistive channel region formed on a semiconductor thin film layer, the thickness of the channel comprising the entire thin film thickness; and

an insulator layer deposited on said channel surface with a gate region formed on a gate material deposited on said insulator layer, said gate region receiving a gate voltage comprised of;

a first level that modulate said channel resistance to a substantially non-conductive state by fully depleting majority carriers from said thin film layer in the channel region; and

a second level that modulate said channel resistance to a substantially conductive state by at least partially accumulating majority carriers near the gate surface of the thin film layer in said channel region.