Methods and apparatus for packaging integrated circuit devices

• US 7,265,440 B2
• Filed: 05/10/2005
• Issued: 09/04/2007
• Est. Priority Date: 06/16/2003
• Status: Expired due to Term

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Katraro, Reuven, Aksenton, Julia, Zilber, Gil, Oganesian, Vage
• Primary Examiner(s): LEE, HSIEN MING
• Application Number:
  US11/125,624
• Publication Number:
  US 20050205977A1
• Time in Patent Office: 847 Days
• Field of Search: 438106-110, 438/113, 257/678, 257/690, 257/684
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/02319 by using a preform
• CPC Class Codes: H01L 2224/02321 Reworking
• CPC Class Codes: H01L 2224/02335 Free-standing redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Claims

1. A packaged chip, comprising:

a chip having a front surface, an active region at the front surface and a conductive pad at the front surface conductively connected to the active region;

a packaging layer having an inner surface confronting the active region of the chip, the inner surface spaced from at least a portion of the active region to define a gap, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface;

a conductive interconnect extending from the conductive pad along at least one of the edge surfaces and along the outer surface.

2. A packaged chip as claimed in claim 1, wherein the chip includes a plurality of the conductive pads and the packaged chip includes a plurality of the conductive interconnects, the conductive interconnects including conductors extending from the conductive pads along the at least one edge surface.

3. A packaged chip as claimed in claim 2, wherein the plurality of conductive pads extend from underneath the packaging layer to beyond the edge surfaces of the packaging layer.

4. A packaged chip as claimed in claim 1, wherein the packaging layer consists essentially of semiconductor material.

5. A packaged chip as claimed in claim 4, further comprising insulation overlying the outer surface of the packaging layer, the at least one conductive interconnect overlying the insulation.

6. A packaged chip as claimed in claim 5, wherein the insulation includes a dielectric layer, the dielectric layer including at least one material selected from the group consisting of epoxy, silicon oxide, solder mask, silicon nitride, silicon oxynitride, polyimide, parylene, polynaphthalenes, fluorocarbons and acrylates.

7. A packaged chip as claimed in claim 1, wherein the inner surface is defined by a recess in the packaging layer.

8. A packaged chip as claimed in claim 1, wherein the packaging layer is a chip-scale packaging layer.

9. A method of fabricating a plurality of packaged chips, comprising:

a) assembling a device wafer including a plurality of chips having front surfaces with a packaging layer overlying the front surfaces, each chip including an active region at the front surface and at least one conductive pad at the front surface conductively connected to the active region, the packaging layer having a inner surface confronting the active region, the inner surface spaced from at least a portion of the active region to define a gap, the packaging layer having an outer surface remote from the inner surface and a plurality of edge surfaces extending away from the outer surface;

b) after step a), forming conductive interconnects to the chips, each conductive interconnect including a contact at the outer surface conductively interconnected to the at least one conductive pad of one of the chips by a conductor extending along a wall of at least one channel in the packaging layer; and

c) severing the device wafer along dicing lanes into a plurality of packaged chips.

10. A method as claimed in claim 9, further comprising the step of forming the at least one channel in the packaging layer before the step (b).

11. A method as claimed in claim 9, wherein the step (c) is performed after the step (b).

12. A method as claimed in claim 9, wherein the step (b) includes depositing a metal to form the conductors extending along the wall of the at least one channel.

13. A method as claimed in claim 12, wherein the packaging layer includes a plate having an area greater than combined area of at least some of the plurality of chips of the device wafer, the step (a) includes joining the device wafer with the plate, and the step (b) includes forming the at least one channel in the plate.

14. A method as claimed in claim 13, wherein the at least one channel includes a plurality of channels extending through the plate, the plurality of channels being elongated in directions of the dicing lanes, the dicing lanes being exposed by the channels.

15. A method as claimed in claim 14, wherein at least one conductive pad of the chip extend beyond walls of the channels.

16. A method as claimed in claim 9, wherein the packaging layer includes a semiconductor.

17. A method as claimed in claim 9, further comprising forming insulation overlying the outer surface and the wall of the packaging layer and the step (b) includes forming the at least one conductive interconnect over the insulation.

18. A method as claimed in claim 9, wherein inner surfaces are defined by recesses in the packaging layer.