Integrated circuit testing module

• US 7,265,570 B2
• Filed: 12/14/2005
• Issued: 09/04/2007
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Inapac Technology Incorporated (Rambus Inc.)
• Inventors: Ong, Adrian E.
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US11/304,445
• Publication Number:
  US 20060150046A1
• Time in Patent Office: 629 Days
• Field of Search: None
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/31922 Timing generation or clock distribution G01R31/3191 takes precedence
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment is configured to operate. In order to do so, the testing interface includes components configured for generating addresses and test data to be provided to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent.

Claims

1. A system comprising:

one or more input components configured to receive signals from an automated testing equipment at a first clock frequency, the automated testing equipment being configured to test an integrated circuit;

an address generating component configured to generate addresses responsive to the signals received from the automated testing equipment;

one or more data generating components configured to generate test data responsive to the signals received from the automated testing equipment, the test data to be delivered to the addresses generated by the address generating component; and

one or more output components configured to convey the generated test data to the generated addresses within the integrated circuit at a second clock frequency, the integrated circuit being separable from the one or more output components, the second clock frequency being a higher frequency than the first clock frequency.

2. The system of claim 1, further comprising one or more data receiving components configured to receive data from the integrated circuit at the second clock frequency and to communicate to the automated testing equipment in response to the received data at the first clock frequency.

3. The system of claim 2, wherein the one or more data receiving components are configured to compress the received data using a data test pattern.

4. The system of claim 2, wherein the one or more data receiving components are configured to compare the received data to an expected result and to use an output of this comparison to communicate to the automated testing equipment.

5. The system of claim 1, wherein the one or more data generating components are further configured to generate the test data responsive to the addresses .generated by the address generating component.

6. The system of claim 1, wherein the one or more output components include a command scheduler configured to schedule the delivery of a command to the integrated circuit.

7. The system of claim 6, wherein the command scheduler is further configured to schedule the delivery of the command according to clock cycles of the second clock frequency.

8. The system of claim 6, wherein the command scheduler is configured to schedule the delivery of the command responsive to the identity of a preceding command.

9. The system of claim 1, wherein the one or more input components and the one or more output components are included in a test module, the test module being one of a plurality of test modules included in a test array configured for testing a plurality of integrated circuits.

10. The system of claim 9, wherein the test array includes a memory configured to store parameters for testing the plurality of integrated circuits, the memory being shared by the plurality of test modules.

11. The system of claim 1, wherein the address generating component and the one or more data generating components are detachable from the automated testing equipment.

12. The system of claim 1, further comprising the automatic testing device configured for testing the integrated circuit and coupled to the one or more input components.

13. The system of claim 1, further comprising the integrated circuit.

14. The system of claim 1, wherein the integrated circuit is a memory device.

15. The system of claim 1, wherein the integrated circuit is one of a plurality of separate integrated circuits that are tested using the one or more output components.

16. A method comprising:

attaching an automated testing equipment to a test module;

attaching an integrated circuit to be tested to the test module;

configuring the test module for testing of the integrated circuit;

receiving test signals from the automated testing equipment at the test module at a first clock frequency;

generating test addresses within the test module responsive to the test signals received from the automated testing equipment;

generating test data within the test module responsive to the test signals received from the automated testing equipment; and

sending the generated test data to the generated test addresses within the integrated circuit at a second clock frequency, the second clock frequency being a higher frequency than the first clock frequency.

17. The method of claim 16, further comprising

receiving signals from the integrated circuit at the second clock frequency, the received signals being responsive to the test data sent to the integrated circuit, and

sending a communication from the test module to the automated testing equipment in response to the signals received from the integrated circuit.

18. The method of claim 17, wherein the communication is generated by compressing the received signals responsive to a test pattern used in generating the test data within the test module.

19. The method of claim 17, wherein the communication is generated by comparing the signals received from the integrated circuit with an expected result.

20. The method of claim 17, wherein the communication is generated by comparing a compressed version of the signals received from the integrated circuit with an expected result.

21. The method of claim 16, further comprising detaching the test module from the integrated circuit, and attaching a second integrated circuit to the test module for testing of the second integrated circuit.

22. The method of claim 16, wherein generating the test data is responsive to whether one of the generated test addresses is ODD or EVEN.

23. The method of claim 16, further comprising delivering commands from the test module to the integrated circuit using a command scheduler.

24. The method of claim 16, further comprising delivering commands from the test module to the integrated circuit using a command scheduler configured to schedule delivery of a command responsive to the identity of a preceding command.

25. The method of claim 16, further comprising delivering commands from the test module to the integrated circuit using a command scheduler configured to deliver the commands using a delay determined in terms of the second clock frequency.

26. A system comprising:

means for connecting a test module between an automated testing equipment and an integrated circuit to be tested;

means for configuring the test module for testing of the integrated circuit;

means for receiving test signals from the automated testing equipment at the test module at a first clock frequency;

means for generating test addresses within the test module responsive to the test signals received from the automated testing equipment;

means for generating test data within the test module responsive to the test signals received from the automated testing equipment;

means for sending the generated test data to the generated test addresses within the integrated circuit at a second clock frequency, the second clock frequency being a higher frequency than the first clock frequency;

means for receiving signals from the integrated circuit at the second clock frequency, the received signals being responsive to the test data sent to the integrated circuit; and

means for sending a communication from the test module to the automated testing equipment in response to the signals received from the integrated circuit.

27. The system of claim 26, further comprising means for testing a plurality of separate integrated circuits using the test module.