Dynamic clock change circuit

• US 7,265,588 B2
• Filed: 08/17/2005
• Issued: 09/04/2007
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Digi International Inc.
• Original Assignee: Digi International Inc.
• Inventors: Chang, Christopher, Parker, Jeffrey Lewis
• Primary Examiner(s): LE, DON P
• Application Number:
  US11/205,668
• Publication Number:
  US 20070043966A1
• Time in Patent Office: 748 Days
• Field of Search: 326 93- 98, 326/37, 326/38, 326/46
• US Class Current: 326/93
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock change circuit includes enabling a clock change frequency to be accepted while a system is active and clock frequencies are at a low period. The circuit includes generating an enabling signal representing a window of time in which a frequency change is accomplished.

Claims

1. A clock frequency change circuit comprising:

a synchronous counter for receipt of a master clock signal;

a first multiplexer for receipt of an output of the counter, the first multiplexer outputting a clock frequency to a first system clock;

a second multiplexer for receipt of the output of the counter, the second multiplexer outputting a clock frequency to a second system clock; and

a flip flop for generating an enable signal corresponding to a low frequency period of the master clock signal and for enabling a clock change request signal.

2. The circuit of claim 1 wherein the synchronous counter is a 5-bit counter.

3. The circuit of claim 1 further comprising a NOR gate disposed between the counter and the flip flop.

4. The circuit of claim 1 wherein the output of the counter is a frequency signal is divided by an integer value.

5. The circuit of claim 4 wherein the integer value is selected from a group consisting of 2, 4, 8, 16 and 32.