CMOS driver with minimum shoot-through current

• US 7,265,591 B1
• Filed: 12/16/2005
• Issued: 09/04/2007
• Est. Priority Date: 07/15/2004
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Petrofsky, Joseph G.
• Primary Examiner(s): Lam; Tuan T.
• Assistant Examiner(s): Nguyen; Hiep
• Application Number:
  US11/304,820
• Time in Patent Office: 627 Days
• Field of Search: 327/108
• US Class Current: 327/108
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

A CMOS driver with minimum shoot-through current is disclosed. The potential for shoot-through current may be eliminated or reduced with a break-before-make circuit driving an output stage. The break-before-make circuit may include a first logic element followed by a first inverter and a second logic element followed by a second inverter. The inverters may be cross-coupled to one another and/or the internal transistors may be configured with different strengths. The logic elements may be configured to eliminate or reduce potential shoot-through current paths, and the signal inputs may be controlled within a certain voltage range.

Claims

1. A circuit, comprising:

a CMOS driver including an output stage and break-before-make circuit configured to drive the output stage, the break-before-make circuit having a first logic element, and a second logic element cross-coupled to the first logic element; and

a logic circuit configured to provide a first input signal having first and second logic states to a first input in each of the first and second logic elements, and provide a second input signal having first and second logic states to a second input in each of the first and second logic elements, the first logic state of the first input signal having a voltage higher than the voltage of the first logic state of the second input signal, and the second logic state of the first input signal having a voltage higher than the voltage of the second logic state of the second input signal.

2. The circuit of claim 1 wherein the logic circuit comprises a comparator.

3. The circuit of claim 1 wherein the first input of each of the first and second logic elements comprises a PMOS transistor and the second input of each of the first and second logic elements comprises a NMOS.

4. The circuit of claim 3 wherein the logic circuit comprises a NMOS driving circuit including a NMOS transistor having a source configured to be coupled to a power supply return and a drain coupled through a first resistor to a first current source and the NMOS transistors in the break-before-make circuit, the NMOS transistor in the logic circuit further having a gate coupled through a second resistor to its drain, and wherein the logic circuit further comprises a PMOS driving circuit including a PMOS transistor having a source configured to be coupled to a power supply and a drain coupled through a third resistor to a second current source and the PMOS transistors in the break-before-make circuit, the PMOS transistor in the logic circuit further having a gate coupled through a fourth resistor to its drain.

5. The circuit of claim 3 wherein the logic circuit comprises a PMOS driving circuit configured to provide the first input signal to the break-before-make circuit, the PMOS driving circuit comprising a PMOS transistor configured to be coupled to a power supply, and wherein the voltage range between the first and second logic states of the first input signal is centered at a voltage equal to the minimum voltage required to turn off the PMOS transistor in the logic circuit, and wherein the logic circuit further comprises a NMOS driving circuit configured to provide the second input signal to the break-before-make circuit, the NMOS driving circuit comprising a NMOS transistor configured to be coupled to a power supply return, and wherein the voltage range between the first and second logic states of the second input signal is centered at a voltage equal to the minimum voltage to turn on the NMOS transistor in the logic circuit.

6. The circuit of claim 3 wherein each of the first and second logic elements has an enabled state and a disabled state, and wherein the first and second input signals provided by the logic circuit to the first and second logic elements are responsive to a signal input to the logic circuit, each of the first and second logic elements being configured to invert the signal input to the logic circuit in the enabled state, and float its respective output in the disabled state.

7. The circuit of claim 6 wherein the break-before-make circuit further comprises a first inverter having an input coupled to the output of the first logic element, and a second inverter having an input coupled to the output of the second logic element, the first inverter being configured for a connection to a power supply return through the second inverter, and the second inverter being configured for a connection to a power supply through the first inverter.

8. The circuit of claim 3 wherein each of the first and second logic elements has an enabled state and a disabled state, and wherein the first and second input signals provided by the logic circuit to the first and second logic elements are responsive to a signal input to the logic circuit, each of the first and second logic elements being configured to invert the signal input to the logic circuit in the enabled state, and wherein the break-before-make circuit further comprises a first inverter having an input coupled to the output of the first logic element, and a second inverter having an input coupled to the output of the second logic element, the first inverter being configured for a connection to a power supply return through the output of the second inverter, and the second inverter being configured for a connection to a power supply through the output of the first inverter.

9. The circuit of claim 8 wherein each of the first and second logic elements is further configured to float its respective output in the disabled state.