Open loop bandwidth test architecture and method for phase locked loop (PLL)

• US 7,265,633 B1
• Filed: 05/19/2005
• Issued: 09/04/2007
• Est. Priority Date: 06/14/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Stiff, Jonathon
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): JOHNSON, RYAN
• Application Number:
  US11/132,894
• Time in Patent Office: 838 Days
• Field of Search: 331/44, 331/8, 331/14, 331/1.A, 331/16, 331/17, 331/DIG.2, 331/25, 331/18, 324/76.53, 324/76.66, 324/76.68, 324/522, 327/156, 327/157
• US Class Current: 331/16
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (V_CTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (V_CTRL).

Claims

1. A phase locked loop (PLL) circuit, comprising:

a test loop filter, comprising

a resistor-capacitor (RC) network coupled to a control node coupled to a voltage controlled oscillator (VCO), and

a test leg coupled to the RC network that includes a test resistance, and at least one test controllable impedance path in series with the test resistance that provides a high impedance in a non-test mode and a low impedance in a test mode.

2. The PLL circuit of claim 1, wherein:

the test controllable impedance path comprises a transistor.

3. The PLL circuit of claim 1, wherein:

is the RC network comprises a load resistance and a first filter capacitor in series with the load resistance between the control node and the first power supply node; and

the test leg is coupled in series with the load resistance and in parallel with the first filter capacitor.

4. The PLL circuit of claim 3, wherein:

the load resistance is coupled to the first filter capacitor at a filter node; and

the test leg includes the test resistance coupled to the first filter node and the test controllable impedance path is coupled between the test resistance and a first power supply node.

5. The PLL circuit of claim 1, wherein:

the test leg further includes an offset voltage circuit coupled in series with the test resistance and test controllable impedance path.

6. The PLL circuit of claim 1, wherein:

the test resistance is a variable resistance that is varied in the test mode.

7. The PLL circuit of claim 1, further including:

an adjustable current supply that provides a selectable current to the control node in the test mode.

8. The PLL circuit of claim 7, wherein:

the adjustable current supply comprises part of a charge pump circuit that provides a current supply based on a phase difference signal in the non-test mode.

9. The PLL circuit of claim 1, further including:

a phase detector circuit that provides a phase difference value that is variable according to test input values in the test mode, and a phase difference value that is based on an input signal and feedback signal that is different from the test input values in the non-test mode; and

a charge pump circuit coupled to the control node that provides a current to the control node based on the phase difference value output from the phase detector circuit.

10. The PLL circuit of claim 1, further including:

a phase detector that generates a phase difference value based on a phase difference between an input signal and a feedback signal;

a charge pump coupled between the phase detector and control node that provides a current to the control node based on the phase difference value;

the VCO has an input coupled to the charge pump; and

a feedback path coupled between an output of the VCO and an input of the phase detector that includes a loop switch that opens the feedback path in the test mode to prevent an output signal of the VCO from being coupled to the input of the phase detector.

11. The PLL circuit of claim 1, wherein:

the loop filter is formed in the same integrated circuit substrate as other portions of the PLL circuit.

12. A method of testing a PLL circuit, comprising the steps of:

enabling a test leg with a test signal to draw current through a load resistance of a PLL loop filter and generate a control voltage at an input of a voltage controlled oscillator;

varying the control voltage; and

measuring the output frequency of the PLL for each of the different control voltages.

13. The method of claim 12, wherein:

the PLL circuit is formed in an integrated circuit; and

enabling the test leg comprises turning on a transistor in response to a test signal applied from a source external to the integrated circuit.

14. The method of claim 12, wherein:

varying the control voltage includes providing a first test current of magnitude I to generate one control voltage, and

providing currents having a multiple of I to generate a plurality of other control voltages.

15. The method of claim 12, wherein:

varying the control voltage includes

outputting predetermined different phase difference values from a phase detector and generating test currents in response to each different phase difference value, and

providing the different test currents to the loop filter.

16. The method of claim 12, wherein:

varying the control voltage includes opening a feedback loop of the PLL.

17. The method of claim 12, further including:

performing a linear regression on output frequency measurements and corresponding values used to vary the control voltage.

18. A phase locked loop (PLL) circuit, comprising:

a test loop filter that includes a load resistor coupled to a control voltage node and a test leg that provides a current path through the load resistor that is disabled in a non-test mode and enabled in a test mode; and

a voltage controlled oscillator coupled to the test loop filter that generates an output signal having a frequency determined, at least in part, on a control voltage generated on the control voltage node.

19. The PLL circuit of claim 18, wherein:

the test loop filter includes a load resistor coupled in series with a first load capacitor and a switch element coupled between the load resistor and a power supply node.

20. The PLL circuit of claim 18, further including:

a variable supply current circuit that provides an output current to the test loop filter in a test mode that has a magnitude that can be varied in response to test signals.