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Image processor with noise reduction circuit

  • US 7,265,784 B1
  • Filed: 08/04/2003
  • Issued: 09/04/2007
  • Est. Priority Date: 08/19/2002
  • Status: Active Grant
First Claim
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1. A digital imaging system, comprising:

  • an image sensor comprising a two-dimensional array of pixel elements and an image buffer for storing pixel data of each captured image, said image sensor outputting digital signals on a pixel bus as pixel data representing an image of a scene;

    an interface circuit coupled to receive said pixel data from said pixel bus;

    a frame buffer, in communication with said interface circuit, coupled to store pixel data provided by said interface circuit; and

    an image processor for processing said pixel data stored in said frame buffer to generate image data for displaying said image of said scene,wherein said interface circuit comprises a noise reduction circuit performing signal processing on said pixel data received on said pixel bus for noise reductions wherein said noise reduction circuit performs a multisample averaging operation using a data and exposure time dependent blending coefficient, said noise reduction circuit performs said multisample averaging operation by averaging multiple reads of the same frame of pixel data provided by said image sensor and applying said data and exposure time dependent blending coefficient; and

    wherein said noise reduction circuit calculates new pixel data for each frame of pixel data received using the equation;

    new data=α

    *input data+(1−

    α

    )*old data, where “

    new data”

    represents the final pixel data, “

    input data”

    represents the pixel data of a current frame to be averaged, “

    old data”

    represents pixel data previously averaged, and “

    α



    represents said data and exposure time dependent blending coefficient.

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