Programmable logic device including programmable interface core and central processing unit
First Claim
1. A system comprising a programmable logic device having an embedded microprocessor, wherein the programmable logic device comprises:
- a programmable interface coupled to the microprocessor, wherein the programmable interface includes a core designated by a user;
wherein the programmable interface includes a crosspoint switch for coupling the plurality of devices;
a peripheral bus coupled to the programmable interface via the crosspoint switch;
wherein the crosspoint switch includes a plurality of address/control paths and a corresponding plurality data paths, and the address/control paths include one or more pipeline registers at like locations in the paths, and the data paths include one or more pipeline registers at like locations in the paths;
a plurality of devices including a first subset coupled to the programmable interface and a second subset coupled to the peripheral bus, each device for one of providing information to the microprocessor via the programmable interface, receiving information from the microprocessor via the programmable interface, and communicating with another device via the programmable interface.
1 Assignment
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Accused Products
Abstract
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user. The programmable interface core allows devices, both on and off-chip, to communicate with the CPU. In one embodiment, the programmable interface core includes a crosspoint switch for coupling a plurality of devices and the CPU. Re-programmability of the PLD provides significant flexibility in providing features that can be parameterized based on the user'"'"'s needs and/or associated design. Specifically, these parameterized features can be implemented in programmable resources on the PLD, thereby allowing these features to be modified at any time. Moreover, only those resources actually needed for the programmable interface core need be implemented, thereby allowing the user to optimize use of the remainder of the PLD. Finally, the functions of the processor local bus can be efficiently limited, thereby allowing the PLD to approach the performance level of an ASIC.
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Citations
12 Claims
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1. A system comprising a programmable logic device having an embedded microprocessor, wherein the programmable logic device comprises:
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a programmable interface coupled to the microprocessor, wherein the programmable interface includes a core designated by a user; wherein the programmable interface includes a crosspoint switch for coupling the plurality of devices; a peripheral bus coupled to the programmable interface via the crosspoint switch; wherein the crosspoint switch includes a plurality of address/control paths and a corresponding plurality data paths, and the address/control paths include one or more pipeline registers at like locations in the paths, and the data paths include one or more pipeline registers at like locations in the paths; a plurality of devices including a first subset coupled to the programmable interface and a second subset coupled to the peripheral bus, each device for one of providing information to the microprocessor via the programmable interface, receiving information from the microprocessor via the programmable interface, and communicating with another device via the programmable interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification