Method of storing bit-pattern in plural devices

• US 7,266,661 B2
• Filed: 05/27/2004
• Issued: 09/04/2007
• Est. Priority Date: 05/27/2004
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Walmsley, Simon Robert
• Primary Examiner(s): Elmore; Reba I.
• Application Number:
  US10/854,500
• Publication Number:
  US 20060061795A1
• Time in Patent Office: 1,195 Days
• Field of Search: 711/154, 711/164
• US Class Current: 711/164
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers

Abstract

A method of storing a bit-pattern in each of a plurality of devices having respective memories is provided. The method comprises, for each device, determining a first memory location and storing the bit-pattern at the first memory location. The first memory locations at which the bit-pattern is stored are different in at least a plurality of the respective devices.

Claims

1. A method of storing a bit-pattern in each of a plurality of devices of a system, each of the devices having a memory, the method comprising, for each device:

(a) determining a first memory location which is different than a first memory location in at least a plurality of the other devices; and

(b) storing the bit-pattern at the determined first memory location;

wherein the different first memory locations are determined such that the bit-pattern storage location of all the respective devices cannot be ascertained from the bit-pattern storage location of any one of the devices.

2. A method according to claim 1, wherein step (a) includes randomly selecting the first memory location.

3. A method according to claim 2, wherein step (a) includes selecting the first memory location based on a stochastic process or mechanism.

4. A method according to claim 1, wherein step (a) includes selecting the first memory location from an existing list or sequence of memory locations.

5. A method according to claim 1, wherein the memory is non-volatile memory.

6. A method according to claim 5, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of to first memory location at which the bit-pattern is stored on that device.

7. A method according to claim 1, wherein the first memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices'"'"' respective bit-pattern.

8. A method according to claim 1, wherein the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices'"'"' respective bit-patterns overlap.

9. A method according to claim 1, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective bit-patterns are shuffled, rotated or otherwise ordered differently.

10. A method according to claim 8, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective bit-patterns are shuffled, rotated or otherwise ordered differently.

11. A method according to claim 1, comprising;

applying a function to the first bit pattern and a second bit pattern, thereby to generate a result; and

storing the result in the first memory location, thereby indirectly storing the first bit-pattern.

12. A method according to claim 11, wherein the second bit-pattern is stored with the device.

13. A method according to claim 12, wherein the second bit-pattern is stored in the device in a non-volatile manner.

14. A method according to claim 11, wherein the function is a logical function.

15. A method according to claim 14, wherein the logical function is an XOR function.

16. A method according to claim 15, wherein the first bit-pattern is a key.

17. A method according to claim 11, wherein the second bit pattern was generated randomly.

18. A method according to claim 17, comprising randomly selecting the second bit-pattern.

19. A method according to claim 18, comprising selecting the second bit-pattern based on a stochastic process or mechanism.

20. A method according to claim 11, comprising selecting the second bit-pattern from an existing list or sequence of bit-patterns.

21. A method according to claim 11, wherein the first memory locations of the devices are selected such that, from device to device, tore is no overlap of the positions of at least some of the bits, bytes or characters of the devices'"'"' respective results.

22. A method according to claim 11, wherein the first memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices'"'"' respective results overlap.

23. A method according to claim 11, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective results are shuffled, rotated or otherwise ordered differently.

24. A method according to claim 22, wherein the first memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective results are shuffled, rowed or otherwise ordered differently.

25. A method according to claim 11, wherein the respective second bit-patterns are stored at a second memory location of each of the respective devices, wherein the second memory locations are different in at least a plurality of the respective devices.

26. A method according to claim 25, wherein the second memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices'"'"' respective second bit-patterns.

27. A method according to claim 25, wherein the second memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices'"'"' respective second bit-patterns overlap.

28. A method according to claim 25, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective second bit-patterns are shuffled, rotated or otherwise ordered differently.

29. A method according to claim 27, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respectives second bit-patterns are shuffled, rotated or otherwise ordered differently.

30. A method according to claim 25, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the second bit-pattern is stored on that device.

31. A method according to claim 1, further comprising, for each device:

determining a second memory location; and

storing, at the second memory location, a result of applying a function to the bit-pattern;

wherein the second memory locations are different in at least a plurality of the respective devices.

32. A method according to claim 31, wherein the function is a logical operation.

33. A method according to claim 31, wherein the function is a bit inversion operation.

34. A method according to claim 31, wherein step (a) includes randomly selecting the second memory location.

35. A mehod according to claim 34, wherein step (a) includes selecting the second memory location based on a stochastic process or mechanism.

36. A method according to claim 31, wherein step (a) includes selecting the second memory location from an existing list or sequence of memory locations.

37. A method according to claim 31, wherein the memory is non-volatile memory.

38. A method according to claim 37, the method further comprising storing one or more code segments in the memory of each device, the one or more code segments including data indicative of the second memory location at which the result is stored on that device.

39. A method according to claim 38, wherein the second memory locations of the devices are selected such that, from device to device, there is no overlap of the positions of at least some of the bits, bytes or characters of the devices'"'"' respective results.

40. A method according to claim 38, wherein the second memory locations of the devices are selected such that, from device to device, positions of at least some of the bits, bytes or characters of the devices'"'"' respective results overlap.

41. A method according to claim 31, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective results are shuffled, rotated or otherwise ordered differently.

42. A method according to claim 40, wherein the second memory locations of the devices are selected such that, from device to device, bit, byte or character positions of the devices'"'"' respective results are shuffled, rotated or otherwise ordered differently.

43. A device having a bit-pattern stored in it in accordance with the method of claim 1.

44. A device having a bit-pattern and a result stored in it in accordance with the method of claim 11.

45. A device having a bit-pattern and a result stored in it in accordance with the method of claim 21.

46. A plurality of devices having respective bit-patterns stored in them in accordance with the method of claim 1.

47. A plurality of devices having respective bit-patterns and results stored in them in accordance with the method of claim 11.

48. A plurality of devices having respective bit-patterns and results stored in them in accordance with the method of claim 21.

49. A device having a bit-pattern stored in it in accordance with the method of claim 1.

50. A device having bit-pattern and a result stored in it in accordance with the method of claim 11.

51. A device having a bit-pattern and a result stored in it in accordance with the method of claim 21.

52. A plurality of devices having respective bit patterns stored in them in accordance with the method of claim 1.

53. A plurality of devices having a bit-pattern and a result stored in them in accordance with the method of claim 11.

54. A plurality of devices having a bit-pattern and a result stored in them in accordance with the method of claim 21.

55. A method according to claim 1, implemented in a first entity configured to authenticate a digital signature supplied by a second entity, wherein one of the entities includes a base key and the other of the entities includes a variant key and a bit-pattern, the variant key being based on the result of applying a one way function to the base key and the bit-pattern, the digital signature having been generated by the second entity using its key to digitally signing at least part of data to be authenticated, the first entity being configured to:

(a) receive the digital signature from the second entity;

(b) receive the data; and

(c) authenticate the digital signature based on the received data and the first entity'"'"'s key.

56. A method according to claim 1, implemented in a first entity including:

a first bit-pattern

a non-volatile memory storing resource data,

a first base key for use with at least a first variant key;

a second variant key for use with a second base key, the second variant key being the result of a one way function applied to;

the second base key; and

the first bit-pattern or a modified bit-pattern based on the first bit-pattern.

57. A method according to claim 1, for enabling or disabling a verification process of a first entity in response to a predetermined event, the first entity having at least one associated bit-pattern and at least one variant key, each of the variant keys having been generated by applying a one way function to:

a base key; and

one or more of the at least one bit-patterns, respectively;

or one or more alternative bit patterns, each of the alternative bit-patterns being based on one or the at least one bit-patterns, the method including

(a) determining that the predetermined event has happened; and

(b) enabling or disabling at least one of the first variant keys in response the predetermined event.

58. A method according to claim 1, implemented in a system for enabling authenticated communication between a first entity and at least one other entity, the system including a second entity, wherein:

the first entity and the second entity share transport keys; and

the second entity includes at least one authentication key configured to be transported from the second entity to the first entity using the transport keys, the authentication key being usable to enable the authenticated communication by the first entity.

59. A method according to claim 1, for storing a first bit-pattern in non-volatile memory of a device, the method comprising:

(a) applying a one way function to a second bit-pattern associated with the device, thereby to generate a first result;

(b) applying a second function to the first result and the first bit-pattern, thereby to generate a second result; and

(c) storing the second result in the memory, thereby indirectly storing the first bit-pattern.

60. A method according to claim 1, for storing at least one functionally identical code segment in each of a plurality of devices, each of the devices having a memory, the method comprising, for each device:

(a) determining a first memory location; and

(b) storing a first of the at least one code segments in the memory at the first memory location;

wherein the first memory location is different in at least a plurality of the respective devices.

61. A method according to claim 1, for providing a sequence of nonces (R0, R1, R2. . .) commencing with a current seed of a sequence of seeds (x1, x2, x3, . . .), the method comprising:

(a) applying a one-way function to the current seed, thereby to generate a current nonce;

(b) ouputting the current nonce;

(c) using the current seed to generate a next seed in a sequence of seeds, the seed so generated becoming the current seed; and

(d) repeating steps (a) to (c) as required to generate further nonces in the sequence of nonces.

62. A method according to claim 1, for storing multiple first bit-patterns in non-volatile memory of a device, the method comprising, for each of the first bit-patterns to be stored:

(a) applying a one way function to a third bit-pattern based on a second bit-pattern associated with the device, thereby to generate a first result;

(b) applying a second function to the first result end the first bit-pattern, thereby to generate a second result; and

(c) storing the second result in the memory, thereby indirectly storing the first bit-pattern;

wherein the third bit-patterns used for the respective first bit-patterns are relatively unique compared to each other.