Error recovery strategies for iterative decoders

• US 7,266,750 B1
• Filed: 06/04/2003
• Issued: 09/04/2007
• Est. Priority Date: 07/10/2002
• Status: Expired due to Fees

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Inventors: Shao, Rose, Patapoutian, Ara, Buch, Bruce
• Primary Examiner(s): Torres; Joseph D.
• Application Number:
  US10/454,326
• Time in Patent Office: 1,553 Days
• Field of Search: 714/758, 714/794
• US Class Current: 714/758
• CPC Class Codes: H03M 13/1105 Decoding
• CPC Class Codes: H03M 13/1111 Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
• CPC Class Codes: H03M 13/3738 with judging correct decoding
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/3784 for soft-output decoding of block codes
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6325 Error control coding in combination with demodulation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

An iterative decoder is controlled to iteratively decode a block by performing one or more decoding iterations for the block during a predetermined block time. The iterative decoder is further controlled to perform more decoding iterations for the block during a time in which the hardware of the iterative decoder is available, if the block fails to converge to correct data during the predetermined block time. The iterative decoder uses a parity-check matrix and can be configured to process that parity-check matrix for parallel, sequential or a combination of parallel and sequential (“hybrid”) parity constraint updates.

Claims

1. A method of decoding comprising:

receiving a block of data from a data channel;

directing a hardware decoder to iteratively decode the block, the hardware decoder performing one or more decoding iterations for the block during a predetermined block time associated with the block and ending the decoding iterations at the termination of the predetermined block time; and

controlling the hardware decoder to perform more decoding iterations for the block after the termination of the predetermined block time and during a time in which the hardware decoder would otherwise be idle, if the block fails to converge to correct data during the predetermined block time.

2. The method of claim 1 wherein the hardware decoder comprises a soft output detector and a decoder.

3. The method of claim 2 wherein the decoder comprises an iterative decoder.

4. The method of claim 3 wherein the iterative decoder comprises a Low Density Parity Check (LDPC) decoder.

5. The method of claim 1 wherein controlling comprises:

storing information usable to perform more decoding iterations for the block in a local buffer;

detecting the time during which the hardware decoder would otherwise be idle; and

providing the buffered information to the hardware decoder.

6. The method of claim 5 wherein the data channel comprises a storage device in a data storage system and the time during which the hardware decoder would otherwise be idle comprises overhead time during which the data storage system is reading control information.

7. The method of claim 6 wherein the data storage system comprises a disk drive and the storage device comprises a hard disk.

8. The method of claim 6 wherein the control information comprises servo information.

9. The method of claim 6 wherein the control information comprises header information.

10. The method of claim 6 wherein the control information comprises gap information.

11. The method of claim 5 wherein the time during which the hardware decoder would otherwise be idle comprises overhead time during which the data storage system is seeking a subsequent block in a non-sequential read mode.

12. The method of claim 5 wherein the buffered information comprises information indicative of the state of the iterative decoding of the block at the end of the predetermined block time.

13. The method of claim 5 wherein the buffered information comprises information representing a waveform of the block.

14. The method of claim 5 wherein controlling comprises:

moving the buffered information between the local buffer and a DRAM.

15. The method of claim 5 wherein the time during which the hardware decoder would otherwise be idle comprises head switching time.

16. The method of claim 1 wherein, for each iteration, the hardware decoder performs updates of parity constraints for a predetermined parity-check matrix in a sequential manner.

17. An apparatus comprising:

a controller; and

a hardware decoder coupled to the controller;

the controller operable to direct the hardware decoder to iteratively decode a block of data received from a data channel by performing one or more decoding iterations for the block during a predetermined block time associated with the block and ending the decoding iterations at the termination of the predetermined block time and to control the hardware decoder to perform more decoding iterations for the block after the termination of the associated predetermined block time and during a time in which the hardware decoder would otherwise be idle, if the block fails to converge to correct data during the predetermined block time.

18. The apparatus of claim 17 wherein the hardware decoder comprises a soft detector and a decoder.

19. The apparatus of claim 18 wherein the decoder comprises an iterative decoder.

20. The apparatus of claim 19 wherein the iterative decoder comprises a LDPC decoder.

21. The apparatus of claim 17, further comprising a local buffer to store information usable to perform more decoding iterations and wherein the controller is operable to determine the time during which the hardware decoder would otherwise be idle and provide the buffered information to the hardware decoder.

22. The apparatus of claim 21 wherein the time during which the hardware decoder would otherwise be idle comprises overhead time during which the data storage system is reading control information.

23. The apparatus of claim 22 wherein the control information comprises servo information.

24. The apparatus of claim 22 wherein the control information comprises preamble information.

25. The apparatus of claim 22 wherein the control information comprises postamble information.

26. The apparatus of claim 21 wherein the time during which the hardware decoder would otherwise be idle comprises overhead time during which the data storage system is seeking a subsequent block in a non-sequential read mode.

27. The apparatus of claim 21 wherein the buffered information comprises information indicative of the state of the iterative decoding of the block at the end of the predetermined block time.

28. The apparatus of claim 21 wherein the buffered information comprises information representing a waveform of the block.

29. The apparatus of claim 21 wherein the controller is operable to move the buffered information between the local buffer and DRAM to free up resources of the local buffer.

30. The apparatus of claim 21 wherein the time during which the hardware decoder would otherwise be idle later comprises head switching time.

31. The apparatus of claim 17 wherein, for each iteration, the hardware decoder performs updates of parity constraints for a parity-check matrix in a sequential manner.

32. A disk drive comprising:

a storage device;

a storage controller, coupled to the storage device, to read blocks of data from the storage device, the storage controller including a hardware decoder and a controller to control the hardware decoder; and

wherein the hardware decoder is operable to iteratively decode a block of data read from the storage device, the hardware decoder performing one or more decoding iterations for the block during a predetermined block time associated with the block and ending the decoding interations at the termination of the predetermined block time;

wherein the controller is operable to control the hardware decoder to perform more decoding iterations for the block after the termination of the predetermined block time and during a time in which the hardware decoder would otherwise be idle, if the block fails to converge to correct data during the predetermined block time.

33. The disk drive system of claim 32 wherein the hardware decoder comprises a soft output detector and an iterative decoder.

34. The disk drive system of claim 33 wherein the iterative decoder comprises a LDPC decoder.