Semiconductor device having layered chips

• US 7,268,420 B2
• Filed: 12/23/2004
• Issued: 09/11/2007
• Est. Priority Date: 12/26/2003
• Status: Expired due to Fees

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Hirose, Yukitoshi
• Primary Examiner(s): Weiss; Howard
• Assistant Examiner(s): Rao; Shrinivas H.
• Application Number:
  US11/019,618
• Publication Number:
  US 20050139978A1
• Time in Patent Office: 992 Days
• Field of Search: 257/686, 257/698, 257/773, 257/774, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.

Claims

1. A semiconductor device comprising:

plural semiconductor chips layered one on another; and

plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,

said plural inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,

wherein an electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes, which are immediately adjacent each other, is sandwiched between two of said inter-chip signal electrodes that are immediately adjacent said electrode pair,

wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.

4. The semiconductor device according to claim 1, wherein said semiconductor chips include an interface chip and a plurality of DRAM chips consecutively disposed on said interface chip, and said DRAM chips are connected to an external circuit via said interface chip.

2. A semiconductor device comprising:

plural semiconductor chips layered one on another; and

plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,

said inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,

wherein one of said inter-chip signal electrodes is sandwiched between two immediately adjacent electrode pairs each including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes,

wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.

5. The semiconductor device according to claim 2, wherein said two electrode pairs are aligned in a first direction and further comprising a third electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes, said third electrode pair being aligned in a second direction that is perpendicular to said first direction.

3. A semiconductor device comprising:

plural semiconductor chips layered one on another; and

plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,

said inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,

wherein an electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes is aligned in a first direction and is sandwiched between a pair of inter-chip signal electrodes, which are immediately adjacent each other and aligned in a second direction crossing said first direction,

wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.

6. The semiconductor device according to claim 3, wherein said second direction is perpendicular to said first direction.