Method and apparatus for accessing stored data in a reconfigurable IC

• US 7,268,586 B1
• Filed: 03/15/2005
• Issued: 09/11/2007
• Est. Priority Date: 11/08/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US11/082,230
• Time in Patent Office: 910 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments provide a first interconnect circuit for accessing stored data in a reconfigurable IC. The reconfigurable IC has at least one reconfigurable circuit and a set of storage elements for storing several data sets for the particular reconfigurable circuit. The first interconnect circuit includes second, third, and fourth interconnect circuits, where the fourth interconnect circuit connects to outputs of the second and third interconnect circuits. The second and third interconnect circuits connect to the storage element sets to provide data sets to the fourth interconnect circuit, which, in turn, provides the received data to the particular reconfigurable circuit. The fourth interconnect circuit operates at a different rate than the second and third interconnect circuits. In some embodiments, the stored data sets are configuration data sets for configuring the articular reconfigurable circuit.

Claims

1. A reconfigurable IC comprising:

a) a particular reconfigurable circuit;

b) a set of storage elements for storing a plurality of data sets for the particular reconfigurable circuit; and

c) first, second, and third interconnect circuits, wherein the third interconnect circuit connects to outputs of the first and second interconnect circuits, wherein first and second interconnect circuits connect to the storage element sets to provide data sets to the third interconnect circuit for providing to the particular reconfigurable circuit;

d) wherein the third interconnect circuit operates at a different rate than the first and second interconnect circuits.

2. The reconfigurable IC of claim 1, wherein the third interconnect circuit operates at a faster rate than the first and second interconnect circuits.

3. The reconfigurable IC of claim 2, wherein the third interconnect circuit switchably connects the particular reconfigurable circuit to the first and second interconnect circuits.

4. The reconfigurable IC of claim 2, wherein the first and second interconnect circuits operate at the same rate.

5. The reconfigurable IC of claim 1, wherein each of the first and second interconnect circuits switchably connects to more than one data set.

6. The reconfigurable IC of claim 5, one of the first and second interconnect circuits does not switch between a pair of data sets while the other one of the first and second interconnect circuits switches between a pair of data sets.

7. The reconfigurable IC of claim 6, wherein at any particular time during the operation of the third interconnect circuit, the third interconnect circuit provides the particular reconfigurable circuit with the data set that is being supplied by the first or second interconnect circuit that is not switching at the particular time between two data sets.

8. The reconfigurable IC of claim 7, wherein the third interconnect circuit operates at a faster rate than the first and second interconnect circuits.

9. The reconfigurable IC of claim 1, wherein the data sets are configuration data sets, wherein each configuration data set specifies a particular configuration for the particular reconfigurable circuit.

10. The reconfigurable IC of claim 1 further comprising:

a) a plurality of reconfigurable circuits;

b) for each particular reconfigurable circuit, a multi-tiered set of interconnect circuits with first, second, and third interconnect circuits, each of the first and second interconnect circuits switchably connecting to more than one configuration data set, said third interconnect circuit switchably connecting outputs of the first and second interconnect circuits to the particular reconfigurable circuit.

11. The reconfigurable IC of claim 10, wherein the third interconnect circuit for each particular reconfigurable circuit switches between the outputs of the first and second interconnect circuits at a faster rate than the first and second interconnect circuits switch between different configuration data sets.

12. The reconfigurable IC of claim 1, wherein no intervening circuits exists between each of the first and second interconnect circuits and the third interconnect circuit.

13. The reconfigurable IC of claim 1, wherein at least one intervening circuit exists between each of the first and second interconnect circuits and the third interconnect circuit.

14. The reconfigurable IC of claim 13, wherein the intervening circuit is a pull-up transistor.

15. The reconfigurable IC of claim 13, wherein the intervening circuit is a buffer.

16. A reconfigurable IC comprising:

a) a plurality of reconfigurable circuits;

b) for each particular reconfigurable circuit, a multi-tiered set of interconnect circuits with first, second, and third interconnect circuits, and

c) each of the first and second interconnect circuits controllably connecting to more than one configuration data set for configuring the particular reconfigurable circuit,

d) said third interconnect circuit controllably connecting outputs of the first and second interconnect circuits to the particular reconfigurable circuit,

e) wherein the third interconnect circuit for each particular reconfigurable circuit switches between the outputs of the first and second interconnect circuits at a faster rate than the first and second interconnect circuits switch between different configuration data sets.

17. An electronic device comprising:

a reconfigurable IC comprising;

a plurality of reconfigurable circuits;

for each particular reconfigurable circuit, a multi-tiered set of interconnect circuits with first, second, and third interconnect circuits,

each of the first and second interconnect circuits switchably connecting to more than one configuration data set for configuring the particular reconfigurable circuit,

said third interconnect circuit switchably connecting outputs of the first and second interconnect circuits to the particular reconfigurable circuit,

wherein the third interconnect circuit for each particular reconfigurable circuit switches between the outputs of the first and second interconnect circuits at a faster rate than the first and second interconnect circuits switch between different configuration data sets.

18. The electronic device of claim 17, wherein each configuration data set specifies a particular configuration for the particular reconfigurable circuit.