Architecture for smart LCD panel interface

• US 7,268,755 B2
• Filed: 03/25/2003
• Issued: 09/11/2007
• Est. Priority Date: 03/25/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Selwan, Pierre M.
• Primary Examiner(s): Hjerpe; Richard
• Assistant Examiner(s): FATAHI YAR, MAHMOUD
• Application Number:
  US10/397,925
• Publication Number:
  US 20040189570A1
• Time in Patent Office: 1,631 Days
• Field of Search: 345/87, 345211-213, 345501-522
• US Class Current: 345/87
• CPC Class Codes: G06F 3/1415 with means for detecting differences between the image stored in the host and the images displayed on the displays
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

An architecture for a smart liquid crystal display (LCD) panel interface is described. The architecture enables a circuit to transfer only updated display data to the interface. When there are no display data updates to transfer, the circuit is placed in the lowest power state to reduce power consumption while the interface displays information locally stored.

Claims

1. A system, comprising:

a central processing unit (CPU);

a chipset, wherein the chipset comprises a main memory coupled to a delta engine; and

a panel coupled to the chipset, wherein the panel comprises a liquid crystal display (LCD) coupled to a display buffer, wherein the CPU and the chipset are placed in a lowest power state if the delta engine determines that a stored image frame stored on the display buffer is the same as an updated image frame sent to the chipset by the CPU when the stored image frame is compared to the updated image frame.

2. The system of claim 1, wherein the updated image frame is transferred to the panel by the delta engine if the updated image frame is different than the stored image frame when compared to the stored image frame.

3. The system of claim 1, wherein the stored image frame stored on the display buffer is provided to the LCD while the CPU and the chipset are in the lowest power state until the delta engine transfers an updated image frame to the panel.

4. The system of claim 1, wherein the chipset further comprises a memory controller hub (MCH) coupled to the main memory, wherein the MCH obtains the updated image frame from the main memory, wherein the updated image frame obtained from the main memory is in packet format.

5. The system of claim 4, wherein the chipset further comprises a graphics engine coupled to the MCH, wherein the graphics engine interprets the packet data and updates a corresponding area of a bitmap.

6. The system of claim 1, wherein the panel further comprises a row driver and a column driver coupled to the LCD, wherein the row driver and the column driver display a bitmapped image on the LCD.

7. The system of claim 1, wherein the updated image frame comprises a first line marker (FLM) signal and a line pulse (LP) signal, wherein the FLM signal indicates the start of a new display frame, wherein the LP signal is a line synchronization pulse that latches a line of display data into the column driver.

8. The system of claim 7, wherein the delta engine transfers the updated image frame to the panel when the LP signal is asserted, the LP signal indicating that the updated image frame is different from the stored image frame when compared to the stored image frame.

9. The system of claim 1, wherein the system is a laptop computer.

10. The system of claim 1, wherein the system is a desktop computer.

20. The system of claim 1, wherein the LCD comprises:

a timing controller; and

a receiver coupled to the timing controller, wherein the receiver is configured to receive the updated image frame only if the stored image frame within the display buffer is different from the updated image frame and to transfer the updated image frame to the timing controller, wherein the timing controller drives the updated image frame to a column driver and a row driver, wherein the column driver and the row driver display the updated image frame on the LCD.

21. The circuit of claim 20, wherein the timing controller obtains display data from the display buffer if the receiver does not receive the updated image frame.

22. The circuit of claim 20, wherein the receiver is a low voltage differential swing input/output buffer.

11. A system, comprising:

a chipset having a main memory;

a discrete graphics chip coupled to the chipset, wherein the discrete graphics chip comprises a frame buffer, a delta engine, and a graphics engine, wherein the storage capacity of the frame buffer is less than the storage capacity of the main memory; and

a panel coupled to the discrete graphics chip wherein the panel comprises a liquid crystal display (LCD) coupled to a display buffer, wherein the display buffer stores a stored image frame to be displayed on the LCD, wherein the discrete graphics chip is configured to send an updated image frame to the panel only in response to a determination that the updated image frame is different from the stored image frame.

12. The system of claim 11, wherein the storage capacity of the frame buffer is a function of a resolution and a pixel depth of the LCD.

13. The system of claim 11, wherein the chipset further comprises a memory controller hub (MCH) coupled to the main memory, wherein the MCH obtains a plurality of command signals from the main memory, wherein the MCH transfers the command signals to the discrete graphics chip.

14. The system of claim 13, wherein the command signals comprise a first line marker (FLM) signal and a line pulse (LP) signal, wherein the FLM signal indicates the start of a new display frame, wherein the LP signal is a line synchronization pulse that latches a line of display data into the column driver.

15. The system of claim 14, wherein the image update circuit transmits color updates to the panel when the LP signal is asserted.

16. A method, comprising:

storing a stored image frame on a delay buffer of a liquid crystal display (LCD) panel

generating an updated image frame on a central processing unit (CPU);

transferring the updated image frame through a chipset to a discrete graphics chip comprising a graphics engine, a delta engine, and a frame buffer;

comparing the updated image frame to the stored image frame with the delta engine to determine whether the updated image frame is different than the stored image frame; and

placing the CPU, the chipset, and the discrete graphics chip in a lowest power mode available if the delta engine determines that the updated image frame is the same as the stored image frame.

17. The method of claim 16, further comprising:

changing the CPU, the chipset, and the discrete graphics engine from the lowest power mode available to a higher power mode if the delta engine determines that the updated image frame is different from the stored image frame.

18. The method of claim 17, further comprising:

sending the updated image frame from the delta engine to the LCD panel.

19. The method of claim 16, further comprising:

obtaining the display data frame to be displayed on the LCD from the display buffer if the IC is in the lowest power state.