Analog buffer memory for high-speed digital image capture
First Claim
Patent Images
1. A digital imaging system comprising:
- an image sensor;
image processing and compression circuits; and
an analog/multi-level memory coupled between said image sensor and said image processing and compression circuits to receive and temporarily store analog data from said image sensor and transmit said analog data to said image processing and compression circuits, wherein said memory comprises;
a plurality of odd numbered write pipelines and a plurality of even numbered write pipelines, each write pipeline comprising;
an array of non-volatile memory cells; and
a write circuit coupled to the array, wherein when started on a programming operation for a selected memory cell in the array, the write circuit applies a first voltage to the selected memory cell to drive a current through the selected memory cell, wherein when an odd numbered pipeline and an even numbered pipeline are both performing programming operations, a selection circuit in the odd numbered pipeline selects the first voltage when a selection circuit in the even numbered pipeline selects a second voltage and a selection circuit in the odd numbered pipeline selects the second voltage when the selection circuit in the even numbered pipeline selects the first voltage.
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Abstract
A digital imaging system uses a high density, high speed analog/multi-level memory to temporarily store image data at high rates for extended periods of time. A portion of the stored data is transmitted for image processing and compression. When image processing and compression on the data are completed, another portion of the stored data is transmitted for processing. As a result, high speed image capture for extended periods is possible because the processing speed of the image processing and compression no longer limit the time required between high speed bursts or the length of a high speed burst.
69 Citations
24 Claims
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1. A digital imaging system comprising:
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an image sensor; image processing and compression circuits; and an analog/multi-level memory coupled between said image sensor and said image processing and compression circuits to receive and temporarily store analog data from said image sensor and transmit said analog data to said image processing and compression circuits, wherein said memory comprises; a plurality of odd numbered write pipelines and a plurality of even numbered write pipelines, each write pipeline comprising; an array of non-volatile memory cells; and a write circuit coupled to the array, wherein when started on a programming operation for a selected memory cell in the array, the write circuit applies a first voltage to the selected memory cell to drive a current through the selected memory cell, wherein when an odd numbered pipeline and an even numbered pipeline are both performing programming operations, a selection circuit in the odd numbered pipeline selects the first voltage when a selection circuit in the even numbered pipeline selects a second voltage and a selection circuit in the odd numbered pipeline selects the second voltage when the selection circuit in the even numbered pipeline selects the first voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A digital imaging system comprising:
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an image sensor; image processing and compression circuits; and an analog/multi-level memory coupled between said image sensor and said image processing and compression circuits to receive and temporarily store analog data from said image sensor and transmit said analog data to said image processing and compression circuits, wherein said memory receives said data at a rate of greater than 10 Mbits/sec for more than 5 seconds and stores more than 50 Mbits of said data and, wherein said memory comprises; a plurality of write pipelines each write pipeline comprising; an array of non-volatile memory cells; and a write circuit coupled to the array, wherein when started on a programming operation for a selected memory cell in the array, the write circuit applies a first voltage to the selected memory cell to drive a current through the selected memory cell; a timing circuit coupled to sequentially start programming operations by the write circuits; and a charge pump that generates the first voltage from a supply voltage and is coupled to the write circuits to supply the first voltage for the programming operations, and wherein the write pipelines comprise; a plurality of odd numbered pipelines; and a plurality of even numbered pipelines, wherein when an odd numbered pipeline and an even numbered pipeline are both performing programming operations, a selection circuit in the odd numbered pipeline selects the first voltage when a selection circuit in the even numbered pipeline selects a second voltage and a selection circuit in the odd numbered pipeline selects the second voltage when the selection circuit in the even numbered pipeline selects the first voltage.
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18. A method for digital imaging, the method comprising:
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converting an image into electrical signals; subsequently storing said image converted into said electrical signals as analog data, wherein storing said image includes; writing said image data into a first and second plurality of write pipelines each comprising an array of non-volatile memory cells and a write circuit coupled to the array, wherein when started on a programming operation for a selected memory cell in the array, the write circuit applies a first voltage to the selected memory cell to drive a current through the selected memory cell, wherein when one of the first plurality of pipelines and an one of the second plurality of pipelines are both performing programming operations, a selection circuit in the pipeline of the first plurality selects the first voltage when a selection circuit in the pipeline of the second plurality selects a second voltage and a selection circuit in the pipeline of the first plurality selects the second voltage when the selection circuit in the pipeline of the second plurality selects the first voltage; and subsequently transmitting portions of said stored analog data for digital signal processing. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification