Trace-pad interface for improved signal quality

• US 7,269,028 B2
• Filed: 12/19/2000
• Issued: 09/11/2007
• Est. Priority Date: 10/16/1997
• Status: Expired due to Term

• Current Assignee: Celestica Incorporated
• Original Assignee: Celestica Incorporated
• Inventors: Csonka, Jacqueline V., Chong, Ignatius T.
• Primary Examiner(s): Vigushin; John B.
• Application Number:
  US09/739,252
• Publication Number:
  US 20020134576A1
• Time in Patent Office: 2,457 Days
• Field of Search: None
• US Class Current: 361/777
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09281 Layout details of a single conductor meander H05K2201/09263; layout details of angles or corners H05K2201/09272
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A method of routing or laying out signal traces on printed wire or circuit board in order to improve signal transmission quality. The method includes routing a given signal trace such that it is electrically connected to a rectangular corner of a substantially wider component pin pad and forms an angle of approximately 135 degrees with the proximate sides of the pad, thereby minimizing the impedance discontinuity at the interface or junction of the signal trace and pad and hence minimizing the reflection of the digital signal at the interface or junction.

Claims

1. The apparatus for a signal-triggered digital circuit, said apparatus comprising:

a signal source for generating a digital signal;

an input receiver, said input receiver receiving said digital signal for said digital circuit and being responsive to triggering induced by said digital signal;

a conducting interface;

a conducting signal path, said conducting signal path being electrically connected to said conducting interface at a corner thereof, said conducting interface being electrically connected to said input receiver, said signal path carrying said digital signal thereover, said conducting signal path having a length which is at least ⅙

th of a transition electrical length of said digital signal carried thereover, said transition electrical length constituting a transient time of said digital signal multiplied by a propagation speed of said digital signal over said conducting signal path, and wherein said transient time of the said digital signal is selected from a group comprising a rise time thereof and a fall time thereof; and

wherein said conducting interface is substantially rectangular in planar view and said conducting signal path connected thereto as aforesaid has a longitudinal centerline axis which forms an angle in a range of 110 to 160 degrees with respect to a side of said conducting interface to which said conducting signal path is connected to thereby produce a reduced reflection of said digital signal at said connection between said conducting interface and said conducting signal path when compared to a connection wherein said angle has a value of 90 degrees.

2. The apparatus according to claim 1, wherein said conducting signal path has a length which is at least said transition electrical length of said digital signal carried thereover.

3. The apparatus according to claim 1, wherein said angle in a range of 110 to 160 degrees is an angle of 135 degrees.

4. The apparatus according to claim 3, further comprising a circuit substrate, wherein said input receiver and said conducting interface are located on said circuit substrate.

5. The apparatus according to claim 4, wherein said circuit substrate comprises a printed circuit board and wherein said conducting interface is a pad and said conducting signal path is a trace.

6. The apparatus according to claim 5, wherein said pad is substantially square in planar view.

7. The apparatus according to claim 5, wherein said trace has a width which is ⅕

th of a width of said pad to which said trace is connected.

8. The apparatus according to claim 5, wherein when said input receiver is mounted to said pad, said trace has a thickness which is in a range of ⅕

th to ⅙

th of a thickness of said pad to which said trace is connected.

9. The apparatus according to claim 5, wherein when said input receiver is mounted to said pad, said pad has a width of 22 mils and a thickness in a range of 6 mils to 7 mils, and wherein said trace has a width of 4 mils and a thickness of 1.2 mils.

10. The apparatus according to claim 5, wherein the apparatus is a memory system which further comprises a memory device, wherein said signal source is a memory controller which generates digital signals in the form of control signals carried by said trace, and wherein said input receiver is located within said memory device.

11. The apparatus according to claim 10, wherein said circuit substrate further comprises a slot and wherein said memory system further comprises a memory module on which said memory device is located, said memory module being a dual in-line memory module (DIMM) comprising an edge connector, said DIMM being connected to said memory controller by said edge connector connecting to said slot.

12. The circuit substrate for a signal-triggered digital circuit, said circuit substrate comprising:

a conducting interface, substantially rectangular in planar view, for electrical connection to an input receiver, said input receiver receiving a digital signal over said digital circuit and being responsive to triggering induced by said digital signal;

a conducting signal path having a width which is ⅕

th of a width of said conducting interface, said conducting signal path being connected to said conducting interface, said signal path carrying said digital signal thereover, said conducting signal path having a thickness which is in a range of ⅕

th to ⅙

th of a thickness of the conducting interface to which said conducting signal path is connected; and

wherein said conducting signal path connected to said conducting interface has a longitudinal centerline axis which forms an angle in a range of 110 to 160 degrees with respect to a side of the conducting interface to which said conducting signal path is connected to thereby produce a reduced reflection of said digital signal at said connection between said conducting interface and said conducting signal path when compared to a connection wherein said angle has a value of 90 degrees.

13. The circuit substrate according to claim 12, wherein said conducting interface is substantially square in planar view.

14. The circuit substrate according to claim 12, wherein when said input receiver is mounted to said conducting interface, said conducting interface has a width of 22 mils and a thickness in a range of 6 mils to 7 mils, and wherein said conducting signal path has a width of 4 mils and a thickness of 1.2 mils.

15. The circuit substrate according to claim 12, wherein said conducting signal path is connected to the conducting interface at a corner thereof.

16. The circuit substrate according to claim 15, wherein said conducting signal path has a length which is at least ⅙

th of a transition electrical length of said digital signal carried thereover, said transition electrical length constituting a transient time of said digital signal multiplied by a propagation speed of said digital signal over said conducting signal path, and wherein said transient time of said digital signal is selected from a group comprising a rise time thereof and a fall time thereof.

17. The circuit substrate according to claim 16, wherein said conducting signal path has a length which is at least said transition electrical length of said digital signal carried thereover.

18. The circuit substrate according to claim 15, wherein said angle in a range of 110 to 160 degrees is an angle of 135 degrees.

19. The circuit substrate according to claim 18, wherein said circuit substrate comprises a printed circuit board, said conducting interface is a pad and said conducting signal path is a trace.

20. The circuit substrate according to claim 19, said circuit substrate further comprising an input receiver and a signal source for generating said digital signal.

21. The circuit substrate according to claim 20, said circuit substrate further comprising a memory device, wherein said signal source is a memory controller which generates digital signals in the form of control signals carried by said trace, and wherein said input receiver is located within said memory device.

22. The circuit substrate according to claim 21, wherein said circuit substrate further comprises a slot and wherein said memory system further comprises a memory module on which said memory device is located, said memory module being a dual in-line memory module (DIMM) comprising an edge connector, said DIMM being connected to said memory controller by said edge connector connecting to said slot.

23. The apparatus for a signal-triggered digital circuit of a memory system device, said apparatus comprising:

a memory controller signal source for generating a digital control signal;

an input receiver located within said memory device, said input receiver receiving said digital signal for said digital circuit and being responsive to triggering induced by said digital signal;

a conducting inter face;

a conducting signal path, said conducting signal path being electrically connected to said conducting interface at a corner thereof said conducting interface being electrically connected to said input receiver, said signal path carrying said digital signal thereover, said conducting signal path having a length which is at least ⅙

^th of a transition electrical length of said digital signal carried thereover, said transition electrical length constituting a transient time of said digital signal multiplied by a propagation speed of said digital signal over said conducting signal path, said transient time of the said digital signal being selected from a group comprising a rise time thereof and a fall time thereof; and

wherein said conducting interface is substantially rectangular in planar view and said conducting signal path connected thereto as aforesaid has a longitudinal centerline axis which forms an angle in a range of 110 to 160 degrees with respect to a side of said conducting interface to which said conducting signal path is connected to thereby produce a reduced reflection of said digital signal at said connection between said conducting interface and said conducting signal path when compared to a connection wherein said angle has a value of 90 degrees.

24. The apparatus according to claim 23, wherein said conducting signal path has a length which is at least said transition electrical length of said digital signal carried thereover.

25. The apparatus according to claim 23, wherein said angle in a range of 110 to 160 degrees is an angle of 135 degrees.

26. The apparatus according to claim 25, further comprising a circuit substrate, wherein said conducting interface and said conducting signal path are located on said circuit substrate.

27. The apparatus according to claim 26, wherein said circuit substrate comprises a printed circuit board and wherein said conducting interface is a pad and said conducting signal path is a trace.

28. The apparatus according to claim 27, wherein said pad is substantially square in planar view.

29. The apparatus according to claim 27, wherein said trace has a width which is ⅕

th of a width of said pad to which said trace is connected.

30. The apparatus according to claim 27, wherein when said input receiver is mounted to said pad, said trace has a thickness which is in a range of ⅕

th to ⅙

th of a thickness of said pad to which said trace is connected.

31. The apparatus according to claim 27, wherein when said input receiver is mounted to said pad, said pad has a width of 22 mils and a thickness in a range of 6 mils to 7 mils, and wherein said trace has a width of 4 mils and a thickness of 1.2 mils.

32. The apparatus according to claim 26, wherein said circuit substrate further comprises a slot and wherein said memory system further comprises a memory module on which said memory device is located, said memory module being a dual in-tine memory module (DIMM) comprising an edge connector, said DIMM being connected to said memory controller by said edge connector connecting to said slot.

33. The circuit substrate for a signal-triggered memory device digital circuit, said circuit substrate comprising:

a conducting interface, substantially rectangular in planar view, for electrical connection to an input receiver of the memory device, said input receiver receiving a digital control signal over said digital circuit and being responsive to triggering induced by said digital control signal;

a conducting signal path having a width which is ⅕

th of a width of said conducting interface, said conducting signal path being connected to said conducting interface, said signal path carrying said digital control signal thereover, said conducting signal path having a thickness which is in the range of ⅕

^th to ⅙

^th of a thickness of the conducting interface to which said conducting signal path is connected; and

wherein said conducting path connected to said conducting interface has a longitudinal centerline axis which forms an angle in a range of 110 to 160 degrees with respect to a side of the conducting interface to which said path is connected to thereby produce a reduced reflection of said digital control signal at said connection between said conducting interface and said conducting path when compared to a connection wherein said angle has a value of 90 degrees.

34. The circuit substrate according to claim 33, wherein said conducting interface is substantially square in planar view.

35. The circuit substrate according to claim 33, wherein when said input receiver is mounted to said conducting interface, said conducting interface has a width of 22 mills and a thickness in a range of 6 mils to 7 mils, and wherein said conducting signal path has a width of 4 mils and a thickness of 1.2 mils.

36. The circuit substrate according to claim 33, wherein said conducting signal path is connected to the conducting interface at a corner thereof.

37. The circuit substrate according to claim 36, wherein said conducting signal path has a length which is at least ⅙

th of a transition electrical length of said digital signal carried thereover, said transition electrical length constituting a transient time of said digital signal multiplied by a propagation speed of said digital signal over said conducting signal path, and wherein said transient time of said digital signal is selected from a group comprising a rise time thereof and a fall time thereof.

38. The circuit substrate according to claim 37, wherein said conducting signal path has a length which is at least said transition electrical length of said digital signal carried thereover.

39. The circuit substrate according to claim 36, wherein said angle in a range of 110 to 160 degrees is an angle of 135 degrees.

40. The circuit substrate according to claim 39, wherein said circuit substrate comprises a printed circuit board, said conducting interface is a pad and said conducting signal path is a trace.

41. The circuit substrate according to claim 40, said circuit substrate further comprising a signal source for generating said digital control signal.

42. The circuit substrate according to claim 41, wherein said circuit substrate further comprises a slot and wherein said memory device farther comprises a memory module on which said memory device is located, said memory module being a dual in-line memory module (DIMM) comprising an edge connector, said DIMM being connected to said memory device by said edge connector connecting to said slot.