Floating gate memory with split-gate read transistor and split gate program transistor memory cells and method for making the same

• US 7,269,063 B2
• Filed: 05/12/2006
• Issued: 09/11/2007
• Est. Priority Date: 02/24/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chih, Yeu-Der
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/433,653
• Publication Number:
  US 20060221682A1
• Time in Patent Office: 487 Days
• Field of Search: 365/185.1, 365/185.05, 365/185.23
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Variations in memory array and cell configuration are shown, which eliminate punch-through disturb, reverse-tunnel. Several configurations are shown which range from combined and separate source lines for each row of cells, a two transistor cell containing a read transistor and a program transistor connected by a merged floating gate, and a two transistor cell where the program transistor has an extra implant to raise the Vt of the transistor to protect against punch-through disturb. A method is also described to rewrite disturbed cells, which were not selected to be programmed.

Claims

1. A floating gate memory array, comprising:

a) an array of floating gate memory cells,

b) a source line coupled to cells in a row of said array,

c) a word line coupled to control gates of transistors of said memory cells in the row of said array, and

d) a read bit line and a program bit line connecting between said memory cells in each column of said array,

wherein a split gate read transistor, a split gate program transistor and a spare split gate transistor form said memory cells.

2. The memory array of claim 1, wherein said word line for the row of memory cells ln said array is segmented and each segment is driven by a word line driver to allow simultaneous memory operations on a number of cells fewer in quantity than that of a complete row.

3. The memory array of claim 1, wherein each row of memory cells in said array is coupled to a unique source line.

4. The memory array of claim 3, wherein said read bit line and said program bit line are merged into one bit line connecting between memory cells in a column.

5. The memory array of claim 1, further comprising:

a) a split gate read transistor and a split gate program transistor forming said memory cells,

b) a floating gate of said read transistor connected to the floating gate of said program transistor and thereby merging the two floating gates,

c) said read bit line connected to a drain of the read transistor,

d) said program bit line connected to the drain of the program transistor.

6. The memory array of claim 5, wherein said program transistor is given an extra implant to increase threshold voltage to prevent punch-through.

7. The memory array of claim 1, further comprising:

a) floating gate of said read transistor connected to the floating gate of said program transistor and thereby merging the two floating gates,

b) said read bit line connected to a drain of the read transistor,

c) said program bit line formed by a first program bit line and a second program bit line,

d) said first program bit line connected to the drain of the split gate program transistor,

e) said second program bit line connected to the drain of the spare split gate transistor.

8. The memory array of claim 7, wherein said memory cell in an adjacent row of a column is formed with the first program bit line connected to the drain of the spare split gate transistor and the second program bit line connected to the drain of the split gate program transistor.

9. The memory array claim 7, wherein said program transistor, said read transistor and said spare transistor are formed with a thin cell.

10. The memory array of claim 7, wherein said memory cells are formed with said split gate read transistor and said split gate program transistor, whereby the first program bit line is connected to the drain of said program transistor and the second program bit line is connected to the program transistor in said memory cell of an adjacent row of the column.

11. The memory array of claim 10, wherein said program transistor is formed with a thin cell and said read transistor is formed with a fat cell.

12. A floating gate memory array, comprising:

a) an array of floating gate memory cells,

b) a source line coupled to cells in a row of said array,

c) a word line coupled to control gates of transistors of said memory cells in said row of said array, and

d) a read bit line and a program bit line connecting between said memory cells in each column of said array, wherein;

a split gate read transistor, a split gate program transistor and a spare split gate transistor form said memory cells,

a floating gate of said read transistor is connected to the floating gate of said program transistor thereby merging the two floating gates,

said read bit line is connected to a drain of said read transistor,

said program bit line is formed by a first program bit line and a second program bit line,

said first program bit line is connected to the drain of said split gate program transistor, and

said second program bit line is connected to the drain of said spare split gate transistor.