Programming memory devices

• US 7,269,066 B2
• Filed: 05/11/2005
• Issued: 09/11/2007
• Est. Priority Date: 05/11/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Louie, Benjamin, Yip, Aaron, Han, Jin-Man, Nguyen, Dzung H., Nazarian, Hagop A.
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US11/126,790
• Publication Number:
  US 20060256620A1
• Time in Patent Office: 853 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.19
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

Claims

1. A method of programming a target memory cell of a memory device, comprising:

programming a plurality of initial programming voltages into the memory device after fabrication of the memory device;

programming a step voltage into the memory device after fabrication of the memory device;

selecting one of the plurality of the programmed initial programming voltages;

applying a programming voltage substantially equal to the selected one of the plurality of the programmed initial programming voltages to a word line that includes the target memory cell;

determining whether the target memory cell is programmed; and

increasing the programming voltage by the programmed step voltage if it is determined that the target memory cell is not programmed.

2. The method of claim 1, wherein programming a step voltage into the memory device after fabrication of the memory device comprises programming a plurality of step voltages into the memory device after fabrication of the memory device and selecting one of the plurality of step voltages.

3. The method of claim 1 further comprises applying a pass voltage to word lines that do not include the target memory cell while applying the programming voltage to the word line that includes the target memory cell, wherein the pass voltage is insufficient for programming memory cells and activates memory cells of the word lines that do not include the target memory cell.

4. The method of claim 3, wherein the pass voltage is selectable after fabrication of the memory device.

5. The method of claim 4, wherein the pass voltage is selected from a plurality of pass voltages.

6. The method of claim 3 further comprises setting a length of a time allowed for a voltage applied to word lines that do not include the target memory cell and a voltage applied to the word line that includes the target memory cell to increase from an initial level to the pass voltage.

7. The method of claim 6, wherein the length of a time is selectable after fabrication of the memory device.

8. The method of claim 7, wherein setting the length of the time comprises selecting the length of time from a plurality of lengths of time.

9. The method of claim 1 further comprises applying a voltage to a source line selectively coupled, by a source select gate, to a NAND string of memory cells that includes the target memory cell.

10. The method of claim 9, wherein applying a voltage to the source line comprises applying Vcc to the source line.

11. The method of claim 1 further comprises applying a voltage to a drain select line coupled to a control gate of a drain select gate that selectively couples a bit line to a NAND string of memory cells that includes the target memory cell.

12. The method of claim 11, wherein applying the voltage to the drain select line comprises increasing the voltage to the drain select line from a first voltage level to a second voltage level and decreasing the voltage to the drain select line from the second level to a third voltage level, wherein the third voltage level is applied to the drain select line while applying the programming voltage to the word line that includes the target memory cell.

13. The method of claim 12, wherein the third voltage level is selectable after fabrication of the memory device.

14. The method of claim 13, wherein the third voltage level is selected from a plurality of third voltage levels.

15. The method of claim 12, wherein the second voltage level is Vcc.

16. The method of claim 15, wherein the third voltage is between Vss and Vcc.

17. The method of claim 1 further comprises applying a voltage to a source select line coupled to a control gate of a source select gate that selectively couples a source line to a NAND string of memory cells that includes the target memory cell.

18. The method of claim 17, wherein applying the voltage to the source select line comprises applying Vss to the source select line.

19. The method of claim 1 further comprises applying a voltage to a bit line selectively coupled to a NAND string of memory cells that includes the target memory cell.

20. The method of claim 19, wherein applying the voltage to the bit line comprises applying an inhibit voltage to the bit line to prevent programming of the target memory cell.

21. The method of claim 1 further comprises setting a length of a time that the programming voltage is applied to the word line that includes the target memory cell.

22. The method of claim 21, wherein the length of a time is selectable after fabrication of the memory device.

23. The method of claim 22, wherein setting the length of the time comprises selecting the length of time from a plurality of lengths of time.

24. A method of programming a target memory cell of a memory device, comprising:

programming a plurality of initial programming voltages into the memory device after fabrication of the memory device;

programming a step voltage into the memory device after fabrication of the memory device;

selecting one of the plurality of the programmed initial programming voltages;

applying a programming voltage substantially equal to the selected one of the plurality of the programmed initial programming voltages to a word line that includes the target memory cell;

applying a pass voltage to word lines that do not include the target memory cell while applying the programming voltage to the word line that includes the target memory cell for turning on memory cells of the word lines that do not include the target memory cell;

applying a voltage to a bit line selectively coupled to a NAND string of memory cells that includes the target memory cell;

determining whether the target memory cell is programmed; and

increasing the programming voltage by the programmed step voltage if it is determined that the target memory cell is not programmed.

25. The method of claim 24, wherein applying the voltage to the bit line comprises applying about 0 volts to the bit line.

26. The method of claim 24, wherein applying the voltage to the bit line comprises applying an inhibit voltage to the bit line to prevent programming of the target memory cell.

27. The method of claim 24 further comprises applying a voltage to a drain select line coupled to a control gate of a drain select gate that selectively couples the bit line to the NAND string that includes the target memory cell, wherein the voltage applied to the drain select line is selectable after fabrication of the memory device.

28. The method of claim 24 further comprises setting a length of a time allowed for a voltage applied to word lines that do not include the target memory cell and a voltage applied to the word line that includes the target memory cell to increase from an initial level to the pass voltage, wherein the length of time is selectable after fabrication of the memory device.

29. The method of claim 24 further comprises setting a length of a time that the programming voltage is applied to the word line that includes the target memory cell, wherein the length of time is selectable after fabrication of the memory device.

30. The method of claim 24 further comprises applying Vss to a source select line coupled to a control gate of a source select gate that selectively couples a source line to the NAND string of memory cells that includes the target memory cell.

31. The method of claim 24 further comprises applying Vcc to a source line selectively coupled, by a source select gate, to the NAND string of memory cells that includes the target memory cell.

32. The method of claim 24 further comprises programming the pass voltage into the memory device after fabrication of the memory device.

33. The method of claim 32, wherein programming the step voltage comprises programming a plurality of step voltages into the memory device after fabrication of the memory device and selecting one of the plurality of step voltages and wherein the pass voltage is selected from a plurality of pass voltages.

34. A memory device, comprising:

an array of memory cells;

a first register for storing a value corresponding to an initial programming voltage;

a second register for storing a value corresponding to a voltage step; and

control circuitry coupled to the array of memory cells and the first and second registers;

wherein the control circuitry is adapted to iteratively apply a programming voltage to a control gate of a target memory cell during programming of the target memory cell;

wherein the control circuitry is adapted to apply a programming voltage substantially equal to the initial programming voltage on a first iteration;

wherein the control circuitry is adapted to increase the programming voltage by an amount substantially equal to the voltage step during successive iterations; and

wherein the first and second registers are programmable after fabrication.

35. The memory device of claim 34, wherein the first and second registers are two-bit registers.

36. The memory device of claim 34, wherein the control circuitry is adapted to apply a pass voltage to control gates of non-target memory cells.

37. The memory device of claim 36 further comprises a third register coupled to the control circuitry for storing a value corresponding to the pass voltage.

38. The memory device of claim 37, wherein the third register is programmable after fabrication.

39. The memory device of claim 37, wherein the third register is a two-bit register.

40. The memory device of claim 36, wherein the control circuitry is adapted to set a length of a time allowed for a voltage applied to the control gates of non-target memory cells and a voltage applied to the control gate of the target memory cell to increase from an initial level to the pass voltage.

41. The memory device of claim 40 further comprises a third register coupled to the control circuitry for storing a value corresponding to the length of time allowed for a voltage applied to the control gates of non-target memory cells and a voltage applied to the control gate of the target memory cell to increase from an initial level to the pass voltage.

42. The memory device of claim 41, wherein the third register is a two-bit register.

43. The memory device of claim 34, wherein the control circuitry is adapted to set a length of the time interval during which the programming voltage is applied to the control gate of the target memory cell.

44. The memory device of claim 43 further comprises a third register coupled to the control circuitry for storing a value corresponding to the length of a time interval during which the programming voltage is applied to the control gate of the target memory cell.