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Method and apparatus for simultaneous differential data sensing and capture in a high speed memory

  • US 7,269,075 B2
  • Filed: 01/07/2003
  • Issued: 09/11/2007
  • Est. Priority Date: 07/07/2000
  • Status: Expired due to Term
First Claim
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1. A differential input latch for use in a Dynamic Random Access memory (DRAM), comprising:

  • a) a differential input stage circuit for receiving a pair of differential input data signals to generate a pair of output signals at a respective first and second nodes;

    b) an amplifying element for amplifying said output signals at said first and second nodes;

    c) a latch element for at least temporarily storing said respective amplified output signals at said first and second output nodes; and

    ,d) a circuitry for dynamically enabling and disabling said differential input stage in response to an enable signal and a clock signal.

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