Method and apparatus for simultaneous differential data sensing and capture in a high speed memory

• US 7,269,075 B2
• Filed: 01/07/2003
• Issued: 09/11/2007
• Est. Priority Date: 07/07/2000
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Demone, Paul
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US10/337,346
• Publication Number:
  US 20030156461A1
• Time in Patent Office: 1,708 Days
• Field of Search: 365/189.05, 365/205, 365/190, 365/233
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A differential data sensing and capture circuit, includes a differential input stage circuit for receiving respective ones of said differential data signals and having first and second output nodes. A latch element is provided, having first and second complementary inputs coupled to receive signals from said respective first and second output nodes. A gating circuit dynamically enables and disables a clock signal to the differential input stage in response to an enable signal, such that power consumption in said differential input stage is conserved. In a further embodiment the enable signal is a complementary clock input signal.

Claims

1. A differential input latch for use in a Dynamic Random Access memory (DRAM), comprising:

a) a differential input stage circuit for receiving a pair of differential input data signals to generate a pair of output signals at a respective first and second nodes;

b) an amplifying element for amplifying said output signals at said first and second nodes;

c) a latch element for at least temporarily storing said respective amplified output signals at said first and second output nodes; and

,

d) a circuitry for dynamically enabling and disabling said differential input stage in response to an enable signal and a clock signal.

3. The differential input latch as claimed in claim 1, said differential input stage circuit comprising a pair of cross-coupled N-channel transistors, having their sources coupled to a clock input signal and their drains coupled to respective n-channel transistors for receiving said respective ones of said input data signals.

4. The differential input latch as claimed in claim 1, wherein said latch element comprises a pair of cross-coupled NAND gates.

2. A method for differential data sensing and capture in a Dynamic Random Access Memory (DRAM), comprising the steps of:

a) receiving a pair of differential input signals at a differential input stage circuit, said differential input stage having first and second output nodes;

b) amplifying the signals at said first and second output nodes;

c) temporarily storing said first and second output nodes in a latch element having first and second complimentary latch inputs; and

,

d) selectively enabling and disabling said differential input stage in response to an enable signal and a clock signal.

5. A differential input latch for use in a Dynamic Random Access memory (DRAM), comprising:

a) a differential input stage circuit for receiving respective ones of a pair of differential input data signals to generate a pair of output signals at respective first and second nodes, indicative of a difference between said pair of differential input data signals;

b) an amplifying element for amplifying said output signals at said first and second nodes;

c) a latch element for latching said respective amplified output signals at said first and second nodes; and

d) a first and second input nodes associated with said differential input stage for dynamically enabling and disabling said differential input stage in response to an enable signal and a clock signal.