Algorithm of bit synchronization for a digital FSK correlation receiver

• US 7,269,233 B2
• Filed: 01/27/2003
• Issued: 09/11/2007
• Est. Priority Date: 01/27/2003
• Status: Expired due to Fees

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Inventors: Chen, Yung-Lung, Shiung, David
• Primary Examiner(s): Ghayour; Mohammed
• Assistant Examiner(s): GHULAMALI, QUTBUDDIN
• Application Number:
  US10/248,519
• Publication Number:
  US 20040146125A1
• Time in Patent Office: 1,688 Days
• Field of Search: 375/305, 375/334, 375/279, 375/272, 375/274, 375/277, 375/278, 375/308, 375/329, 375/331, 370/503, 370/386
• US Class Current: 375/334
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

An algorithm for bit synchronization in a frequency shift keying (FSK) receiver. In the algorithm, a training sequence is received from a transmitter. The training sequence has a plurality of bits. A starting point of a next bit received by the FSK receiver after the training sequence is determined according to peak values of the bits of the training sequence.

Claims

1. A method for bit synchronization in a frequency shift keying (FSK) receiver, the method comprising steps of:

receiving a training sequence from a transmitter, wherein the training sequence having a plurality of bits;

determining peak values corresponding to each of the received plurality of bits of the training sequence in a corresponding test range of each of the received plurality of bits; and

determining a starting point of a next bit received by the FSK receiver after the training sequence according to the peak values;

wherein, the starting point of the next bit received by the FSK receiver is determined by summing the peak values, dividing the summation by a number of the received plurality of bits of the training sequence, and then adding a bias value.

2. The method of claim 1, the each of the received bits being divided into a plurality of points, the peak value being determined according to the points of the bit in the corresponding test range.

3. The method of claim 2, wherein the peak value is a maxima value in the corresponding test range if the bit is “

1”

.

4. The method of claim 2, wherein the peak value is a minima value in the corresponding test range if the bit being “

0”

.

5. The method of claim 1, wherein the bias value is predetermined and set according to a length of the training sequence.

6. The method of claim 1, wherein the bias value is determined and set by summing the number of points of all of the bits in the training sequence, and dividing the summation by the number of the bits.

7. A frequency shift keying (FSK) receiver using the method for bit synchronization as claimed in claim 1.

8. An method for bit synchronization in a frequency shift keying (FSK) receiver, the method comprising steps of:

receiving a training sequence from a transmitter, wherein the training sequence having a plurality of bits; and

determining a starting point of a next bit received by the FSK receiver after the training sequence according to peak values of the bits of the training sequence, wherein the starting point of the next bit received by the FSK receiver is determined by summing the peak values, dividing the summation by a number of the received plurality of bits of the training sequence, and then adding a bias value.

9. The method of claim 8, the each of the bits being divided into a plurality of paints, the peak value being determined according to the plurality of points of the bit in a corresponding test range.

10. The method of claim 9, wherein the peak value is a maxima value in the in the corresponding test range if the bit is “

1” and

the peak value is a minima value in the corresponding test range if the bit being “

0”

.

11. The method of claim 8, wherein the bias value is predetermined and set according to a length of the training sequence.

12. The method of claim 8, wherein the bias value is determined and set by summing the number of points of all of the bits in the training sequence, and dividing the summation by the number of the bits.

13. A frequency shift keying (FSK) receiver using the method for bit synchronization as claimed in claim 8.