Manufacturing process of a stacked semiconductor device

• US 7,269,897 B2
• Filed: 12/23/2003
• Issued: 09/18/2007
• Est. Priority Date: 12/24/2002
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Frezza, Giovanni
• Primary Examiner(s): Trinh; Minh
• Assistant Examiner(s): Nguyen; Donghai D
• Application Number:
  US10/745,296
• Publication Number:
  US 20040163240A1
• Time in Patent Office: 1,365 Days
• Field of Search: 298/34, 29836-840, 298/54, 294/12, 294/17, 298/30, 29831-833, 298/35, 156/60, 156/300, 156/89.11, 156/89.15, 257/686, 257/777, 257/E21.705, 257/E25.01, 257/778, 438106-108, 438112-114, 438/118, 438/460, 438/464
• US Class Current: 29/832
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49131 by utilizing optical sighting device
• CPC Class Codes: Y10T 29/49135 : and shaping, e.g., cutting or bending, etc.
• CPC Class Codes: Y10T 29/49137 : Different components

Abstract

A manufacturing process of a stacked semiconductor device, comprising the following steps: integrating a plurality of electronic devices in a plurality of active areas realized in a semiconductor wafer; distributing an adhesive layer on active areas, splitting the semiconductor wafer into a plurality of first dies, each one comprising at least one of the active areas; mounting the plurality of first dies, which are already equipped with the adhesive layer, on a support; and mounting a plurality of second dies on the adhesive layer.

Claims

1. A process of manufacturing stacked semiconductor devices comprising:

integrating a plurality of electronic devices in a plurality of active areas, the plurality of active areas being integrated in a semiconductor wafer;

distributing a first adhesive layer on the active areas;

splitting the semiconductor wafer into a plurality of first dies, each first die comprising at least one of the active areas and a respective portion of the first adhesive layer; and

mounting a plurality of second dies on the respective portions of the first adhesive layer;

mounting the plurality of first dies on a support;

forming openings in the first adhesive layer to expose contact pads; and

electrically connecting the support with the exposed contact pads, wherein the openings are formed prior to splitting the semiconductor wafer into the first dies and the electrically connecting step is performed after splitting the semiconductor wafer into the first dies.

2. The process of claim 1, wherein the first adhesive layer is a polymeric silicone layer.

3. The process of claim 1, wherein the first adhesive layer is distributed according to a screen-printing technique.

4. The process of claim 1, wherein the first adhesive layer is distributed according to a photo-definition technique.

5. The process of claim 1, further comprising:

mounting a second semiconductor wafer, comprising a plurality of dummy dies, on the first adhesive layer and the first wafer, before splitting the semiconductor wafer so that the dummy dies contact the first dies; and

placing a plurality of second adhesive layers on the plurality of dummy dies, respectively, before mounting the plurality of second dies on the second adhesive layers.

6. The process of claim 1, wherein said first adhesive layer comprises a welding layer or an eutectic glass layer.

7. The process of claim 1 wherein each first die is fully covered with the first adhesive layer.

8. The process of claim 1 wherein the first adhesive layer is a silicone layer or an epoxy layer.

9. A process of manufacturing stacked semiconductor devices comprising:

integrating a plurality of electronic devices in a plurality of active areas, the plurality of active areas being realized integrated in a semiconductor wafer;

distributing a plurality of adhesive layers on the active areas, respectively;

splitting the semiconductor wafer into a plurality of first dies after distributing the adhesive layers on the active layers, each first die comprising at least one of the active areas and the respective adhesive layer; and

mounting a plurality of second dies directly on the respective adhesive layers;

mounting the plurality of first dies on a support;

forming openings in the adhesive layers to expose contact pads; and

electrically connecting the support with the exposed contact pads, wherein the openings are formed prior to splitting the semiconductor wafer into the first dies and the. electrically connecting step is performed after splitting the semiconductor wafer into the first dies.

10. The process of claim 9, wherein the adhesive layers are distributed according to a screen-printing technique.

11. The process of claim 9, wherein the adhesive layers are distributed according to a photo-definition technique.

12. The process of claim 9 wherein the adhesive layer is a silicon layer or an epoxy layer.