Method of fabricating non-volatile memory
First Claim
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1. A method comprising:
- forming a gate dielectric layer on a substrate;
forming a floating gate layer on the gate dielectric layer;
forming a dielectric layer pattern on the floating gate layer, the dielectric layer pattern exposing a region of the floating gate layer;
forming a first thermal oxide layer on the exposed region of the floating gate layer;
removing the first thermal oxide layer from the floating gate layer;
forming a dielectric sidewall on a sidewall of the dielectric layer pattern;
forming a coupling dielectric layer on the exposed region of the floating gate layer;
forming a program gate in contact with the coupling dielectric layer and the dielectric sidewall; and
partially removing the coupling dielectric layer and the floating gate layer until a portion of the gate dielectric layer is exposed, thereby forming a trench region extending through the coupling dielectric layer and the floating gate layer.
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Abstract
In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.
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Citations
35 Claims
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1. A method comprising:
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forming a gate dielectric layer on a substrate; forming a floating gate layer on the gate dielectric layer; forming a dielectric layer pattern on the floating gate layer, the dielectric layer pattern exposing a region of the floating gate layer; forming a first thermal oxide layer on the exposed region of the floating gate layer; removing the first thermal oxide layer from the floating gate layer; forming a dielectric sidewall on a sidewall of the dielectric layer pattern; forming a coupling dielectric layer on the exposed region of the floating gate layer; forming a program gate in contact with the coupling dielectric layer and the dielectric sidewall; and partially removing the coupling dielectric layer and the floating gate layer until a portion of the gate dielectric layer is exposed, thereby forming a trench region extending through the coupling dielectric layer and the floating gate layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A method comprising:
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forming a semiconductor substrate having a first junction region and a second junction region; forming an insulated floating gate disposed on the substrate, the floating gate at least partially overlapping the first junction region; forming an insulated program gate disposed on the floating gate, the program gate having a curved upper surface; and forming an insulated erase gate disposed on the substrate and adjacent the floating gate, the erase gate partially overlapping the second junction region. - View Dependent Claims (35)
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Specification