Method of fabricating non-volatile memory

• US 7,271,061 B2
• Filed: 07/21/2005
• Issued: 09/18/2007
• Est. Priority Date: 09/22/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Han, Jeong-Uk, Jeon, Hee-Seog, Yoon, Seung-Beom
• Primary Examiner(s): Pert; Evan
• Application Number:
  US11/187,424
• Publication Number:
  US 20060062069A1
• Time in Patent Office: 789 Days
• Field of Search: 438/257, 438/264
• US Class Current: 438/257
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

Claims

1. A method comprising:

forming a gate dielectric layer on a substrate;

forming a floating gate layer on the gate dielectric layer;

forming a dielectric layer pattern on the floating gate layer, the dielectric layer pattern exposing a region of the floating gate layer;

forming a first thermal oxide layer on the exposed region of the floating gate layer;

removing the first thermal oxide layer from the floating gate layer;

forming a dielectric sidewall on a sidewall of the dielectric layer pattern;

forming a coupling dielectric layer on the exposed region of the floating gate layer;

forming a program gate in contact with the coupling dielectric layer and the dielectric sidewall; and

partially removing the coupling dielectric layer and the floating gate layer until a portion of the gate dielectric layer is exposed, thereby forming a trench region extending through the coupling dielectric layer and the floating gate layer.

2. The method of claim 1, wherein forming the gate dielectric layer comprises forming a thermal oxide to a thickness of about 50 to about 150 Å

.

3. The method of claim 1, wherein forming the floating gate layer comprises depositing a polysilicon layer to a thickness of about 500 to about 1500 Å

.

4. The method of claim 1, wherein forming a dielectric layer pattern comprises forming another dielectric layer on the floating gate layer and patterning the dielectric layer.

5. The method of claim 4, wherein forming another dielectric layer comprises depositing a nitride layer to a thickness of about 2000 to about 4000 Å

.

6. The method of claim 1, further comprising forming another thermal oxide layer on the floating gate layer before forming the dielectric sidewall thereon.

7. The method of claim 6, wherein another thermal oxide layer is formed to a thickness of about 50 to about 150 Å

.

8. The method of claim 1, wherein forming a thermal oxide layer comprises forming a thermal oxide to a thickness of about 500 to about 1500 Å

.

9. The method of claim 1, wherein removing the first thermal oxide layer comprises wet etching.

10. The method of claim 1, wherein removing the first thermal oxide layer comprises forming a substantially rounded region of the floating gate layer adjacent to a sidewall of the dielectric layer pattern.

11. The method of claim 1, wherein forming the dielectric sidewall comprises:

depositing a high temperature oxide; and

anisotropically etching the high temperature oxide.

12. The method of claim 1, wherein the dielectric sidewall is about 500 to about 1500 Å

thick.

13. The method of claim 1, wherein forming the program gate comprises:

depositing polysilicon on the coupling dielectric layer; and

anisotropically etching the deposited polysilicon without using a photolithographic process.

14. The method of claim 13, wherein the polysilicon is deposited to a thickness of about 1500 to about 3000 Å

.

15. The method of claim 1, further comprising removing an upper portion of the program gate concurrently with partially removal of the coupling dielectric layer.

16. The method of claim 15, further comprising an optional thermal oxide layer that covers exposed surfaces of the program gate.

17. The method of claim 16, wherein the thickness of the optional thermal oxide layer is about 50 to about 150 Å

.

18. The method of claim 1, wherein forming the coupling dielectric layer comprises using one selected from the group consisting of a thermal oxidation process, a high temperature oxide CVD process, and a combination of a thermal oxidation process and a medium temperature oxide CVD process.

19. The method of claim 1, further comprising:

ion implanting in the trench region to form a source region in the substrate;

depositing a dielectric material to fill the trench region and cover the dielectric layer pattern;

planarizing the dielectric material until the dielectric layer pattern is exposed; and

removing the dielectric layer pattern to expose a region of the floating gate layer.

20. The method of claim 19, wherein ion implanting comprises ion implanting the impurities at a dose of about 10¹⁵ ions/cm².

21. The method of claim 19, wherein depositing the dielectric material comprises depositing an oxide to a thickness of about 5000 to 10000 Å

using a CVD process.

22. The method of claim 19, wherein removing the dielectric layer pattern comprises wet etching the dielectric layer pattern with phosphoric acid.

23. The method of claim 19, further comprising:

etching the floating gate layer to form a floating gate by using the dielectric material and the dielectric sidewall as a mask without using a photolithographic process.

24. The method of claim 23, wherein etching the floating gate layer comprises anisotropic dry etching.

25. The method of claim 23, further comprising:

removing a portion of the coupling dielectric layer above the floating gate and a portion of the gate dielectric layer below the floating gate to expose a tip of the floating gate;

forming a tunneling dielectric layer on the tip of the floating gate and a sidewall of the floating gate.

26. The method of claim 25, wherein forming the tunneling dielectric layer comprises forming a thermal oxide layer to a thickness of about 50 to about 150 Å

.

27. The method of claim 25, further comprising:

forming an additional tunneling dielectric layer on the tunneling dielectric layer.

28. The method of claim 27, wherein forming the additional tunneling dielectric layer comprises using a CVD process.

29. The method of claim 25, further comprising:

forming an erase gate layer on the substrate;

etching the erase gate layer to form an erase gate with a curved upper surface; and

implanting ions beneath the erase gate layer to form a drain region.

30. The method of claim 29, wherein forming the erase gate layer comprises depositing a polysilicon layer to a thickness of about 150 to about 3000 Å

.

31. The method of claim 29, wherein etching the erase gate layer comprises anisotropic dry etching without using a photolithographic process.

32. The method of claim 29, wherein the program gate includes a substantially vertical surface that is aligned with a substantially vertical surface of the floating gate.

33. The method of claim 29, wherein an upper part of the erase gate extends higher than an upper part of the program gate.

34. A method comprising:

forming a semiconductor substrate having a first junction region and a second junction region;

forming an insulated floating gate disposed on the substrate, the floating gate at least partially overlapping the first junction region;

forming an insulated program gate disposed on the floating gate, the program gate having a curved upper surface; and

forming an insulated erase gate disposed on the substrate and adjacent the floating gate, the erase gate partially overlapping the second junction region.

35. The method of claim 34, wherein forming an insulated erase gate comprises forming the insulated erase gate having a curved upper surface.