Ultra-thin semiconductors bonded on glass substrates

• US 7,271,445 B2
• Filed: 08/31/2004
• Issued: 09/18/2007
• Est. Priority Date: 05/21/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Primary Examiner(s): Purvis; Sue A.
• Assistant Examiner(s): Wilson; Scott R.
• Application Number:
  US10/931,553
• Publication Number:
  US 20050023612A1
• Time in Patent Office: 1,113 Days
• Field of Search: 257347-354, 257/507, 257/E21.32, 257/E21.561, 257/E27.112, 438/149
• US Class Current: 257/347
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors

Abstract

A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to the glass substrate. The thin semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. An ultra-thin silicon layer bonded to a glass substrate, selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate, provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Claims

1. A semiconductor structure comprising:

a borosilicate glass substrate; and

a semiconductor layer bonded directly in contact to the borosilicate glass substrate without an alkali concentration associated with anodic bonding, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer.

2. The semiconductor structure of claim 1, wherein the thickness is less than a thickness correlated to onset of yield for the semiconductor layer at a maximum temperature-induced strain of the semiconductor layer.

3. The semiconductor structure of claim 1, wherein the semiconductor layer is a silicon layer.

4. A semiconductor structure comprising:

a glass substrate, the glass substrate being selected from a group consisting of a fused silica substrate and a fused quartz substrate; and

a semiconductor layer bonded directly in contact to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer.

5. The semiconductor structure of claim 4, wherein the thickness is less than a thickness correlated to onset of yield for the semiconductor layer at a maximum temperature-induced strain of the semiconductor layer.

6. An electronic device comprising:

a semiconductor layer bonded directly in contact to a borosilicate glass substrate without an alkali concentration associated with anodic bonding, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer; and

circuitry in the semiconductor layer.

7. The electronic device of claim 6, wherein the semiconductor layer is a silicon layer.

8. An electronic device comprising:

a semiconductor layer bonded directly in contact to a glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer and the glass substrate being selected from a group consisting of a fused silica substrate and a fused quartz substrate; and

circuitry in the semiconductor layer.

9. The electronic device of claim 8, wherein the monocrystalline semiconductor layer is disposed across the glass substrate.

10. An electronic device comprising:

a semiconductor layer bonded directly in contact to a glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer and the glass substrate being selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate; and

circuitry in the semiconductor layer, wherein the semiconductor layer is a silicon layer having a thickness of about 0.1 microns.

11. The semiconductor structure of claim 10, wherein the monocrystalline semiconductor layer is disposed across the glass substrate.

12. An electronic device comprising:

a semiconductor layer bonded to a glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer and the glass substrate being selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate; and

circuitry in the semiconductor layer, wherein the semiconductor layer is a silicon layer having a thickness less than 0.1 microns.

13. The electronic device of claim 12, further including an oxide layer between the silicon layer and the glass substrate.

14. A memory comprising:

an array of memory cells; and

an address decoder coupled to the array, wherein the array and the address decoder are formed on a semiconductor structure including;

a borosilicate glass substrate, and

a semiconductor layer bonded directly in contact to the borosilicate glass substrate without an alkali concentration associated with anodic bonding, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer.

15. The memory of claim 14, wherein the semiconductor layer has a thickness of about 0.1 microns.

16. A memory comprising:

an array of memory cells; and

an address decoder coupled to the array, wherein the array and the address decoder are formed on a semiconductor structure including;

a glass substrate, the glass substrate being selected from a group consisting of a fused silica substrate and a fused quartz substrate; and

a semiconductor layer bonded directly in contact to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer.

17. The memory of claim 16, wherein the memory is a dynamic random access memory.

18. A memory comprising:

an array of memory cells; and

an address decoder coupled to the array, wherein the array and the address decoder are formed on a semiconductor structure including;

a glass substrate, the glass substrate being selected from a group consisting of fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate; and

a semiconductor layer bonded to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer, wherein the semiconductor layer is a silicon layer having a thickness less than 0.1 microns.

19. The semiconductor structure of claim 18, further including an oxide layer between the silicon layer and the glass substrate.

20. An electronic system comprising:

a controller;

a bus; and

an electronic device coupled to the controller by the bus, the electronic device including;

a borosilicate glass substrate;

a semiconductor layer bonded directly in contact to the borosilicate glass substrate without an alkali concentration associated with anodic bonding, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer; and

a circuit on the semiconductor layer.

21. The electronic system of claim 20, wherein the semiconductor layer has a thickness less than 0.1 microns.

22. An electronic system comprising:

a controller;

a bus; and

an electronic device coupled to the controller by the bus, the electronic device including;

a glass substrate, the glass substrate being selected from a group consisting of a fused silica substrate and a fused quartz substrate;

a semiconductor layer bonded directly in contact to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer; and

a circuit on the semiconductor layer.

23. The electronic system of claim 22, wherein the monocrystalline semiconductor layer is disposed across the glass substrate.

24. An electronic system comprising:

a controller;

a bus; and

an electronic device coupled to the controller by the bus, the electronic device including;

a glass substrate, the glass substrate being selected from a group consisting of fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate;

a semiconductor layer bonded directly in contact to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer; and

a circuit on the semiconductor layer, wherein the semiconductor layer is a silicon layer having a thickness of about 0.1 microns.

25. The memory of claim 24, wherein the monocrystalline semiconductor layer is disposed across the glass substrate.

26. An electronic system comprising:

a controller;

a bus; and

an electronic device coupled to the controller by the bus, the electronic device including;

a glass substrate, the glass substrate being selected from a group consisting of fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate;

a semiconductor layer bonded to the glass substrate, the semiconductor layer having a thickness such that the semiconductor layer does not yield due to temperature-induced strain at device processing temperatures, the semiconductor layer being a monocrystalline semiconductor layer; and

a circuit on the semiconductor layer, wherein the semiconductor layer is a silicon layer having a thickness less than 0.1 microns.

27. The electronic system of claim 26, wherein the electronic device includes an oxide layer between the silicon layer and the glass substrate.

28. An electronic system comprising:

a processor;

a system bus; and

a memory device coupled to the processor by the system bus, the memory device including;

a glass substrate, the glass substrate being selected from a group consisting of fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate;

a silicon layer bonded to the glass substrate, the silicon layer having a thickness less than 0.1 microns, the silicon layer being a monocrystalline silicon layer; and

a memory circuit on the semiconductor layer.

29. The electronic system of claim 28, wherein the glass substrate is a fused silica substrate or a fused quartz substrate.

30. The electronic system of claim 28, wherein the glass substrate is a borosilicate glass substrate.

31. The electronic system of claim 28, further including an oxide layer between the silicon layer and the glass substrate.

32. The electronic system of claim 28, wherein the silicon layer is disposed across the glass substrate.