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Post passivation interconnection schemes on top of the IC chips

  • US 7,271,489 B2
  • Filed: 10/12/2004
  • Issued: 09/18/2007
  • Est. Priority Date: 10/15/2003
  • Status: Active Grant
First Claim
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1. A circuit component comprising:

  • a semiconductor substrate;

    an ESD circuit in or on said semiconductor substrate;

    an I/O circuit in or on said semiconductor substrate;

    a first metallization structure over said semiconductor substrate;

    a passivation layer over said first metallization structure; and

    a second metallization structure over said passivation layer, wherein said second metallization structure connects said ESD circuit and said I/O circuit, and wherein a signal stimuli is provided to said ESD circuit and said I/O circuit through said second metallization structure.

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