Post passivation interconnection schemes on top of the IC chips

• US 7,271,489 B2
• Filed: 10/12/2004
• Issued: 09/18/2007
• Est. Priority Date: 10/15/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Chou, Chien-Kang, Chou, Chiu-Ming
• Primary Examiner(s): Picardat; Kevin M.
• Application Number:
  US10/962,963
• Publication Number:
  US 20060076687A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/690, 257/700, 257/691, 257/920, 257/773, 257/774, 438/614, 438/615, 438/616, 438/622, 438/631, 438/637, 438/638
• US Class Current: 257/773
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A circuit component comprising:

a semiconductor substrate;

an ESD circuit in or on said semiconductor substrate;

an I/O circuit in or on said semiconductor substrate;

a first metallization structure over said semiconductor substrate;

a passivation layer over said first metallization structure; and

a second metallization structure over said passivation layer, wherein said second metallization structure connects said ESD circuit and said I/O circuit, and wherein a signal stimuli is provided to said ESD circuit and said I/O circuit through said second metallization structure.

2. The circuit component of claim 1, wherein said I/O circuit comprises a driver.

3. The circuit component of claim 1, wherein said I/O circuit comprises a receiver.

4. The circuit component of claim 1, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 microns.

5. The circuit component of claim 1, wherein said passivation layer comprises an oxynitride layer having a thickness greater than 0.3 microns.

6. The circuit component of claim 1, wherein said second metallization structure comprises electroplated gold.

7. The circuit component of claim 1, wherein said second metallization structure comprises electroplated copper.

8. The circuit component of claim 1, wherein said second metallization structure comprises electroplated silver.

9. The circuit component of claim 1, wherein said second metallization structure comprises electroplated palladium.

10. The circuit component of claim 1, wherein said second metallization structure comprises electroplated nickel.

11. The circuit component of claim 1, wherein said second metallization structure comprises a metal line having a thickness of greater than 2 microns.

44. The circuit component of claim 1, wherein said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated copper.

45. The circuit component of claim 1, wherein said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated gold.

46. The circuit component of claim 1, wherein said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising palladium.

47. The circuit component of claim 1, wherein said signal stimuli comprises a clock signal.

48. The circuit component of claim 1, wherein said signal stimuli comprises an address signal.

49. The circuit component of claim 1, wherein said signal stimuli comprises a data signal.

12. A circuit component comprising:

a semiconductor substrates;

a first I/O circuit in or on said semiconductor substrate;

a second I/O circuit in or on said semiconductor substrate;

a first metallization structure over said semiconductor substrate, wherein said first metallization structure is connected to said first I/O circuit;

a second metallization structure over said semiconductor substrate, wherein said second metallization structure is connected to said second I/O circuit;

a passivation layer over said first and second metallization structures; and

a third metallization structure over said passivation layer, wherein said third metallization structure connects said first and second metallization structures, and wherein a signal stimuli is provided to said first and second I/O circuits through said third metallization structure.

13. The circuit component of claim 12, wherein said first I/O circuit comprises a driver.

14. The circuit component of claim 12, wherein said first I/O circuit comprises a receiver.

15. The circuit component of claim 12, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 microns.

16. The circuit component of claim 12, wherein said passivation layer comprises an oxynitride layer having a thickness greater than 0.3 microns.

17. The circuit component of claim 12, wherein said third metallization structure comprises electroplated gold.

18. The circuit component of claim 12, wherein said third metallization structure comprises electroplated copper.

19. The circuit component of claim 12, wherein said third metallization structure comprises electroplated silver.

20. The circuit component of claim 12, wherein said third metallization structure comprises electroplated palladium.

21. The circuit component of claim 12, wherein said third metallization structure comprises electroplated nickel.

22. The circuit component of claim 12, wherein said third metallization structure comprises a metal line having a thickness of greater than 2 microns.

50. The circuit component of claim 12, wherein said third metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated copper.

51. The circuit component of claim 12, wherein said third metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated gold.

52. The circuit component of claim 12, wherein said third metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising palladium.

53. The circuit component of claim 12, wherein said signal stimuli comprises a clock signal.

54. The circuit component of claim 12, wherein said signal stimuli comprises an address signal.

55. The circuit component of claim 12, wherein said signal stimuli comprises a data signal.

23. A circuit component comprising:

a semiconductor substrate;

a first internal circuit in or on said semiconductor substrate, wherein said first internal circuit comprises a first signal node;

a second internal circuit in or on said semiconductor substrate, wherein said second internal circuit comprises a second signal node;

a first metallization structure over said semiconductor substrate;

a passivation layer over said first metallization structure; and

a second metallization structure over said passivation layer, wherein said second metallization structure connects said first and second signal nodes, and wherein a first product of resistance of a first portion of said second metallization structure times capacitance of said first portion is smaller than a second product of resistance of a second portion of said first metallization structure times capacitance of said second portion by the range of from 5 times to 10,000 times, said first portion having a same length as said second portion.

24. The circuit component of claim 23, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 microns.

25. The circuit component of claim 23, wherein said passivation layer comprises an oxynitride layer having a thickness greater than 0.3 microns.

26. The circuit component of claim 23, wherein said second metallization structure comprises electroplated gold.

27. The circuit component of claim 23, wherein said second metallization structure comprises electroplated copper.

28. The circuit component of claim 23, wherein said second metallization structure comprises electroplated silver.

29. The circuit component of claim 23, wherein said second metallization structure comprises electroplated palladium.

30. The circuit component of claim 23, wherein said second metallization structure comprises electroplated nickel.

31. The circuit component of claim 23, wherein said second metallization structure comprises a metal line having a thickness of greater than 2 microns.

56. The circuit component of claim 23, wheren said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated copper.

57. The circuit component of claim 23, wherein said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising electroplated gold.

58. The circuit component of claim 23, wherein said second metallization structure comprises a metal line having a thickness of between 2 and 100 microns and comprising palladium.

32. A circuit component comprising:

a semiconductor substrate;

a repeater in or on said semiconductor substrate;

an on-chip driver in or on said semiconductor substrate;

a first metallization structure over said semiconductor substrate;

a passivation layer over said first metallization structure; and

a second metallization structure over said passivation layer, wherein said second metallization structure connects said repeater and said on-chip driver.

33. The circuit component of claim 32, wherein said repeater comprises a driver and a receiver, said driver of said repeater being connected in series to said receiver of said repeater.

34. The circuit component of claim 32, wherein said passivation layer comprises a nitride layer having a thickness greater than 0.3 microns.

35. The circuit component of claim 32, wherein said passivation layer comprises an oxynitride layer having a thickness greater than 0.3 microns.

36. The circuit component of claim 32, wherein said second metallization structure comprises electroplated gold.

37. The circuit component of claim 32, wherein said second metallization structure comprises electroplated copper.

38. The circuit component of claim 32, wherein said second metallization structure comprises electroplated silver.

39. The circuit component of claim 32, wherein said second metallization structure comprises electroplated palladium.

40. The circuit component of claim 32, wherein said second metallization structure comprises electroplated nickel.

41. The circuit component of claim 32, wherein said second metallization structure comprises a metal line having a thickness of greater than 2 microns.

42. The circuit component of claim 32, further comprising a receiver in or on said semiconductor substrate, and a third metallization structure over said metallization structure, wherein said third metallization structure connects said repeater and said receiver.

43. The circuit component of claim 42, further comprising a first internal circuit in or on said semiconductor substrate, and a second internal circuit in or on said semiconductor substrate, wherein said on-chip driver comprises a first contact connected to said first internal circuit and a second contact connected to said repeater, and wherein said receiver comprises a first contact connected to said second internal circuit and a second contact connected to said repeater.