Prognostic cell for predicting failure of integrated circuits
First Claim
1. An integrated circuit (IC) chip, comprising:
- a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and
a prognostic cell that is statistically designed to fail at a designed trigger time t1 under increased operational stress correlated to the operational stress on the useful circuit by a prognostic distance of t2−
t1 ahead of the useful circuit, said cell failure triggering a failure indicator as a predictor of impending failure of the useful circuit.
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Accused Products
Abstract
A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.
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Citations
55 Claims
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1. An integrated circuit (IC) chip, comprising:
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a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and a prognostic cell that is statistically designed to fail at a designed trigger time t1 under increased operational stress correlated to the operational stress on the useful circuit by a prognostic distance of t2−
t1 ahead of the useful circuit, said cell failure triggering a failure indicator as a predictor of impending failure of the useful circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. An integrated circuit (IC) chip, comprising:
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a useful circuit having a component that is subject to failure in response to operational stress, said component having a cumulative failure probability C(t) where t2 equals the time at which the failure probability of the useful circuit'"'"'s component has increased to a fraction f2, and; a prognostic cell that is statistically designed to fail with a cumulative trigger probability P(t) where t1 equals the time at which a fraction f1 of the prognostic cells have triggered under increased operational stress correlated to the operational stress on the useful circuit by a prognostic distance equal to t2−
t1 ahead of the useful circuit, said cell triggering a failure indicator as a predictor of impending failure of the useful circuit. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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43. An integrated circuit (IC) chip, comprising:
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a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and a prognostic cell that is statistically designed to fail at a designed trigger time t1 under increased operational stress by a prognostic distance of t2−
t1 ahead of the useful circuit component, said prognostic cell comprises;a plurality of test devices each having a test component; a coupling circuit that couples the operational stress applied to the useful circuit to the test devices; a stress circuit that increases the operational stress applied to the test devices as a function of the prognostic distance to accelerate deterioration of the test components; and a comparison circuit that compares a performance characteristic of each test component to a baseline, determines whether the stressed test component has failed and when a certain fraction of the plurality fail generates a failure indicator as a predictor of impending failure of the useful circuit. - View Dependent Claims (44, 45, 46, 47)
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48. An integrated circuit (IC) chip, comprising:
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a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and an oversampled prognostic cell with multiple readout capability that is statistically designed to fail at a designed trigger time t1 under increased operational stress by a prognostic distance of t2−
t1 ahead of the useful circuit component, said prognostic cell comprises;a plurality of test devices each having a test component; a coupling circuit that couples the operational stress applied to the useful circuit to the test devices; a stress circuit that increases the operational stress applied to the test devices as a function of the prognostic distance to accelerate deterioration of the test components; and a comparison circuit that compares a performance characteristic of each test component to a baseline, determines whether the stressed test component has failed and generates a failure indicator for each failed test component. - View Dependent Claims (49, 50)
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51. An integrated circuit (IC) chip, comprising:
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a useful MOS device that is subject to possible failure due to a threshold voltage shift at a time t2 in response to operational stress; and a prognostic cell that is statistically designed to fail at a designed trigger time t1 by a prognostic distance of t2−
t1 ahead of the useful MOS device, said cell comprising test and reference MOS devices with different gate bias conditions that place the test MOS device under increased operational stress such that the MOS devices exhibit different threshold voltage shirts and a comparator circuit that generates a failure indicator when the difference in threshold voltages exceeds a preset amount as a predictor of impending failure of the useful MOS device. - View Dependent Claims (52, 53, 54, 55)
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Specification