Prognostic cell for predicting failure of integrated circuits

• US 7,271,608 B1
• Filed: 11/19/2003
• Issued: 09/18/2007
• Est. Priority Date: 11/25/2002
• Status: Expired due to Fees

• Current Assignee: Ridgetop Group, Inc.
• Original Assignee: Ridgetop Group, Inc.
• Inventors: Vermeire, Bert M., Parks, Harold G., Goodman, Douglas L.
• Primary Examiner(s): Karlsen; Ernest
• Assistant Examiner(s): Vazquez; Arleen M.
• Application Number:
  US10/716,686
• Time in Patent Office: 1,399 Days
• Field of Search: 324/760, 324/763, 324/765, 324/158.1, 340/635, 340/653, 702/34
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads

Abstract

A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.

Claims

1. An integrated circuit (IC) chip, comprising:

a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and

a prognostic cell that is statistically designed to fail at a designed trigger time t1 under increased operational stress correlated to the operational stress on the useful circuit by a prognostic distance of t2−

t1 ahead of the useful circuit, said cell failure triggering a failure indicator as a predictor of impending failure of the useful circuit.

2. The IC chip of claim 1, wherein the prognostic cell comprises:

a test device having a test component;

a coupling circuit that couples the operational stress applied to the useful circuit to the test device;

a stress circuit that increases the operational stress applied to the test device to accelerate deterioration of the test component; and

a comparison circuit that compares a performance characteristic of the stressed test component to a baseline performance characteristic, determines whether the stressed test component has failed and generates the failure indicator.

3. The IC chip of claim 2, wherein the useful circuit and the test device are equivalent devices.

4. The IC chip of claim 2, wherein the useful circuit and the test device are different devices with similar components.

5. The IC chip of claim 4, wherein the useful circuit'"'"'s component is a gate insulator of a transistor and the test component is a spacer insulator layer of a capacitor.

6. The IC chip of claim 4, wherein the test component has different dimensions than the useful circuit'"'"'s component to more accurately measure the deterioration of the test component.

7. The IC chip of claim 2, wherein the coupling circuit couples the test device to at least one of a supply voltage, a drive signal or a stress event outside normal operating condition applied to the useful circuit.

8. The IC chip of claim 7, wherein the stress circuit increases said supply voltage, alters said drive signal or prolongs the stress event to increase the operational stress applied to the test device.

9. The IC chip of claim 2, wherein the prognostic cell comprises a plurality of test devices, said comparison circuit triggering the failure indicator when a certain traction of the plurality fail.

10. The IC chip of claim 9, wherein said comparison circuit reads out each test device failure.

11. The IC chip of claim 2, further comprising a reference circuit that is subjected to reduced operation stress to establish the baseline for the performance characteristic.

12. The IC chip of claim 11, wherein the reference circuit is subjected to minimal operational stress.

13. The IC chip of claim 12, wherein the reference circuit is subjected to average operational stress.

14. The IC chip of claim 1, wherein the increased operational stress accelerates an end-of-life failure mechanism of the prognostic cell.

15. The IC chip of claim 1, wherein the increased operational stress is a function of the prognostic distance, the larger the prognostic distance the greater the increased operational stress.

16. The IC chip of claim 15, wherein the increased operational stress applied to the prognostic cell is the same operational stress that is applied to the useful circuit just increased so that the failure of the prognostic cell, although accelerated, tracks the failure of the useful circuit.

17. The IC chip of claim 15, wherein the operational stress comprises use stress and environmental stress.

18. The IC chip of claim 17, wherein the operational stress is increased by an elevated supply voltage, a different bias condition or a modified drive signal applied to the test device.

19. The IC chip of claim 1, wherein the useful circuit component comprises a gate insulator in a MOS device that is subject to failure due to an ESD event, said prognostic cell comprising a test capacitor having an insulator spacer layer, a coupling circuit that couples a supply voltage and the ESD event to the test capacitor, a stress circuit that increases the supply voltage to the test capacitor and prolongs the ESD event, and a comparison sub-circuit that compares the voltage supported across the test capacitor against a baseline voltage to detect degradation of the insulator spacer layer.

20. The IC chip of claim 19, wherein the coupling circuit comprises at least one diode that is forward biased by an ESD event to couple it to the test capacitor and the stress circuit comprises a charge pump that increases the supply voltage and sufficient capacitance to prolong the ESD event across the test capacitor.

21. The IC chip of claim 20, wherein the charge pump is periodically disconnected to allow the voltage across the test capacitor to degrade, said comparison circuit comparing this voltage against the baseline voltage to detect degradation of the insulator spacer layer.

22. The IC chip of claim 1, wherein the useful circuit comprises a MOS device in the IC that is subject to field oxide failure due to radiation effects, said prognostic cell predicts leakage under the field oxide failure comprising at least one of:

a first inverter formed by a current source and a monitor transistor having a gate bias to stress the radiated monitor transistor, said current source being set to an allowed radiation degradation limit for end around leakage between the monitor transistor'"'"'s source and drain;

a second inverter formed by a current source and a monitor transistor having a gate bias to stress the radiated monitor transistor, said current source being set to an allowed radiation degradation limit for device to device leakage in a common well;

a third inverter formed by a current source and a monitor transistor having a gate bias to stress the radiated monitor transistor, said current source being set to an allowed radiation degradation limit for device to a neighboring n-well leakage; and

a comparator generating the failure indicator when any one of the inverters produces an output that inverts with respect to the baseline.

23. The IC chip of claim 1, wherein the useful circuit component is a MOS device that is subject to failure due to a threshold voltage shift based on radiation effects, said prognostic cell comprising test and reference MOS devices with different gate bias conditions so that the MOS devices exhibit different threshold voltage shifts when subjected to ionizing radiation, and a comparator circuit that generates the failure indicator when the difference in threshold voltages exceeds a preset amount.

24. The TC chip of claim 23, wherein a worst case gate bias is applied to the test MOS device and a best case gate bias is applied to the reference MOS device.

25. The IC chip of claim 1, wherein the useful circuit component comprises an insulator layer in the IC chip that is subject to failure based on an insulator electric field, said prognostic cell predicting time dependent dielectric breakdown (TDDB) of the insulator layer and comprising a test capacitor with an insulator spacer layer, a coupling circuit that couples a supply voltage from the host IC to the test capacitor, a stress circuit that increases the supply voltage applied to tile test capacitor to create a stressed insulator electric field, and a comparison circuit that compares the voltage supported across the test capacitor against a baseline voltage to detect degradation of the insulator spacer layer.

26. The IC chip of claim 25, wherein the stress circuit comprises a charge pump that pumps a well containing the test capacitor to create a larger voltage across the insulator spacer layer than the supply voltage.

27. The IC chip of claim 26, wherein the charge pump is periodically disconnected to allow the voltage across the test capacitor to degrade, said comparison circuit comparing this voltage against the baseline voltage to detect degradation of the insulator spacer layer.

28. The IC chip of claim 1, wherein the useful circuit comprises a MOS transistor in the IC, said prognostic cell predicting hot carrier degradation of the MOS transistor and comprising test and reference MOS devices with different gate voltages so that the test and reference MOS transistors exhibit, over time, different threshold voltage shifts, and a comparator circuit that generates the failure indicator when the difference in threshold voltages exceeds a preset amount.

29. The IC chip of claim 28, wherein the gate voltage of the test MOS device is approximately one third of the drain voltage for longer periods than the gate voltage of the reference MOS device.

30. The IC chip of claim 29, wherein the gate voltage of the test MOS device is a triangular wave.

31. The IC chip of claim 1, wherein the useful circuit component comprises interconnect conductors in the IC, said prognostic cell predicting metal migration of the interconnect conductors.

32. An integrated circuit (IC) chip, comprising:

a useful circuit having a component that is subject to failure in response to operational stress, said component having a cumulative failure probability C(t) where t2 equals the time at which the failure probability of the useful circuit'"'"'s component has increased to a fraction f2, and;

a prognostic cell that is statistically designed to fail with a cumulative trigger probability P(t) where t1 equals the time at which a fraction f1 of the prognostic cells have triggered under increased operational stress correlated to the operational stress on the useful circuit by a prognostic distance equal to t2−

t1 ahead of the useful circuit, said cell triggering a failure indicator as a predictor of impending failure of the useful circuit.

33. The IC chip of claim 32, wherein f1 is the tolerable fraction of non-accurate predictions by the prognostic cell and f2 is the tolerable failure traction of the useful circuit'"'"'s component.

34. The IC chip of claim 33, wherein the prognostic cell is stressed so that P(t) reaches a value close to unity before C(t) start to increase appreciably.

35. The IC chip of claim 32, wherein the prognostic cell has a trigger probability density p(t) with a standard deviation that affects an amount of useful lifetime sacrificed by a premature trigger and/or a fraction of missed failure predictions of the useful circuit'"'"'s component by late triggers.

36. The IC chip of claim 35, wherein the fraction f1 is set close to unity so that the fraction of missed failure predictions is small.

37. The IC chip of claim 35, wherein the trigger probability density p(t) overlaps with a failure probability density c(t) of the useful circuit'"'"'s component, said fraction f1 being set so that the prognostic distance is positive and small.

38. The IC chip of claim 35, wherein the prognostic cell comprises a plurality of test devices with test components that fail the same performance characteristic, said cell triggering the failure indicator when a certain fraction of the plurality tail thereby reducing the standard deviation of p(t) and the amount of useful lifetime sacrificed.

39. The IC chip of claim 32, wherein the prognostic cell has a trigger probability density p(t) with a standard deviation that affects the accuracy of triggering the failure indicator, said prognostic cell comprising a plurality of test devices with test components that fail the same performance characteristic, said cell triggering the failure indicator when a certain fraction of the plurality fail thereby reducing the standard deviation of p(t) and improving the accuracy of the failure indicator.

40. The IC chip or claim 32, wherein the useful circuit component is a MOS device that is subject to failure due to a threshold voltage shift based on operational stress, said prognostic cell comprising test and reference MOS devices with different gate bias conditions so that the test MOS device is placed under increased operational stress and the MOS devices exhibit different threshold voltage shifts, and a comparator circuit that generates the failure indicator when the difference in threshold voltages exceeds a preset amount.

41. The IC chip of claim 40, wherein a worst case gate bias is applied to the test MOS device and a best case gate bias is applied to the reference MOS device.

42. The IC chip of claim 32, wherein the useful circuit is a MOS device and said prognostic cell predicts leakage under the field oxide failure of the MOS device, said prognostic cell comprising at least one of:

a first inverter formed by a current source and a monitor transistor having a gate bias to stress the monitor transistor, said current source being set to an allowed degradation limit for end around leakage between the monitor transistor'"'"'s source and drain;

a second inverter formed by a current source and a monitor transistor having a gate bias to stress the monitor transistor, said current source being set to an allowed degradation limit for device to device leakage in a common well;

a third inverter formed by a current source and a monitor transistor having a gate bias to stress the monitor transistor, said current source being set to an allowed degradation limit for device to a neighboring n-well leakage; and

a comparator generating the failure indicator when any one of the inverters produces an output that inverts with respect to a baseline.

43. An integrated circuit (IC) chip, comprising:

a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and

a prognostic cell that is statistically designed to fail at a designed trigger time t1 under increased operational stress by a prognostic distance of t2−

t1 ahead of the useful circuit component, said prognostic cell comprises;

a plurality of test devices each having a test component;

a coupling circuit that couples the operational stress applied to the useful circuit to the test devices;

a stress circuit that increases the operational stress applied to the test devices as a function of the prognostic distance to accelerate deterioration of the test components; and

a comparison circuit that compares a performance characteristic of each test component to a baseline, determines whether the stressed test component has failed and when a certain fraction of the plurality fail generates a failure indicator as a predictor of impending failure of the useful circuit.

44. The IC chip of claim 43, wherein the coupling circuit couples the test device to at least one of a supply voltage, a drive signal or a stress event outside normal operating condition applied to the useful circuit, and the stress circuit increases said supply voltage, alters said drive signal or prolongs the stress event to increase the operational stress applied to the test device.

45. The IC chip of claim 43, wherein said comparison circuit reads out each test device failure.

46. The IC chip of claim 43, further comprising a reference circuit that is subjected to reduced operational stress to establish the baseline for the performance characteristic.

47. The IC chip of claim 43, wherein the test component has a trigger probability density p(t) with a standard deviation that determines an amount of useful lifetime equal to the difference between the designed trigger time t1 and an average actual trigger time tavg sacrificed to achieve the prognostic distance, the number of test devices selected to narrow the standard deviation such that the amount of useful lifetime sacrificed is less than an acceptable amount.

48. An integrated circuit (IC) chip, comprising:

a useful circuit having a component that is subject to possible failure at a time t2 in response to operational stress; and

an oversampled prognostic cell with multiple readout capability that is statistically designed to fail at a designed trigger time t1 under increased operational stress by a prognostic distance of t2−

t1 ahead of the useful circuit component, said prognostic cell comprises;

a plurality of test devices each having a test component;

a coupling circuit that couples the operational stress applied to the useful circuit to the test devices;

a stress circuit that increases the operational stress applied to the test devices as a function of the prognostic distance to accelerate deterioration of the test components; and

a comparison circuit that compares a performance characteristic of each test component to a baseline, determines whether the stressed test component has failed and generates a failure indicator for each failed test component.

49. The IC chip of claim 48, further comprising a reference circuit that is subjected to reduced operational stress to establish the baseline for the performance characteristic.

50. The IC chip of claim 48, wherein the test component has a trigger probability density p(t) with a standard deviation that determines an amount of useful lifetime equal to the difference between the designed trigger time t1 and an average actual trigger time tavg sacrificed to achieve the prognostic distance, the number of test devices selected to narrow the standard deviation such that the amount of useful lifetime sacrificed is less than an acceptable amount.

51. An integrated circuit (IC) chip, comprising:

a useful MOS device that is subject to possible failure due to a threshold voltage shift at a time t2 in response to operational stress; and

a prognostic cell that is statistically designed to fail at a designed trigger time t1 by a prognostic distance of t2−

t1 ahead of the useful MOS device, said cell comprising test and reference MOS devices with different gate bias conditions that place the test MOS device under increased operational stress such that the MOS devices exhibit different threshold voltage shirts and a comparator circuit that generates a failure indicator when the difference in threshold voltages exceeds a preset amount as a predictor of impending failure of the useful MOS device.

52. The IC chip of claim 51, wherein the operational stress is based on an environmental stress and gate bias.

53. The IC Chip of claim 52, wherein all of the MOS devices are subjected to the same environmental stress, said test MOS device being subjected to a different gate bias condition that places it under increased operational stress.

54. The IC chip of claim 53, wherein the environmental stress is exposure to radiation.

55. The IC chip of claim 51, wherein said test and reference MOS device each have a source, a drain and a gate, said comparator connected to measure the voltage difference at the drains, further comprising:

first and second switches to apply said different bias conditions to the gates of said test and reference MOS devices;

third and fourth switches to connect the drains of said test and reference MOS devices to a supply voltage;

fifth and sixth switches to connect the gates to the drains of said test and reference MOS devices; and

seventh and eighth switches to connect the drains of said test and reference MOS devices to respective current sources,

wherein during a stress cycle said first, second, third and fourth switches are closed and said fifth, sixth, seventh and eighth switches are open such that said test and reference MOS devices exhibit different threshold voltage shifts, and

wherein during a measurement cycle, said first, second, third and fourth switches are open and said fifth, sixth, seventh and eighth switches are closed such that said current sources supply current to the respective drains to generate voltages at the drains.