Low-power receiver equalization in a clocked sense amplifier
First Claim
1. A receiver comprising:
- a. a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
b. a first transistor having a first current-handling terminal coupled to the first output terminal, a second current-handling terminal, and a first control terminal coupled to the first input terminal;
c. a second transistor having a third current-handling terminal coupled to the first output terminal, a fourth current-handling terminal, and a second control terminal;
d. a first high-pass filter coupled between the first and second control terminals;
e. a third transistor having a fifth current-handling terminal coupled to the second output terminal, a sixth current-handling terminal, and a third control terminal coupled to the second input terminal;
f. a fourth transistor having a seventh current-handling terminal coupled to the second output terminal, an eighth current-handling terminal, and a fourth control terminal;
g. a second high-pass filter coupled between the third and fourth control terminals; and
h. a regenerative load having a first load input terminal coupled to the first and third current-handling terminals and a second load input terminal coupled to the fifth and seventh current-handling terminals.
1 Assignment
0 Petitions
Accused Products
Abstract
A receiver includes clocked, differential equalization circuitry to compensate for signal attenuation that varies with the frequency of the input signal received over a respective communication channel. The incoming signal is split into filtered and unfiltered signal components. Separate current-steering transistors coupled in parallel amplify the filtered and unfiltered components and sum the results. The filter or filters used to separate the signal components may be tunable, e.g. using voltage-controlled filter components. The ratio of device sizes for the current-steering transistors sets the magnitude of the boost applied to high-frequency components. The embodiments include adjustable or programmable current-steering networks to facilitate adjustments that accommodate the unique characteristics of individual communication channels.
31 Citations
34 Claims
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1. A receiver comprising:
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a. a first input terminal, a second input terminal, a first output terminal, and a second output terminal; b. a first transistor having a first current-handling terminal coupled to the first output terminal, a second current-handling terminal, and a first control terminal coupled to the first input terminal; c. a second transistor having a third current-handling terminal coupled to the first output terminal, a fourth current-handling terminal, and a second control terminal; d. a first high-pass filter coupled between the first and second control terminals; e. a third transistor having a fifth current-handling terminal coupled to the second output terminal, a sixth current-handling terminal, and a third control terminal coupled to the second input terminal; f. a fourth transistor having a seventh current-handling terminal coupled to the second output terminal, an eighth current-handling terminal, and a fourth control terminal; g. a second high-pass filter coupled between the third and fourth control terminals; and h. a regenerative load having a first load input terminal coupled to the first and third current-handling terminals and a second load input terminal coupled to the fifth and seventh current-handling terminals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A receiver comprising:
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a. an input terminal and an output terminal; b. a first transistor having a first current-handling terminal coupled to the output terminal, a second current-handling terminal, and a first control terminal coupled to the input terminal; c. a second transistor having a third current-handling terminal coupled to the output terminal, a fourth current-handling terminal, and a second control terminal; d. a high-pass filter selectively coupled between the first and second control terminals; and e. a switch coupled in series with the high-pass filter; f. wherein the switch comprises a multiplexer having a first multiplexer input terminal coupled to the first control terminal, a second multiplexer input terminal coupled to a reference-voltage node, and a multiplexer output terminal coupled to the second control terminal. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A receiver comprising:
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a. an input terminal, to receive an input signal, and an output terminal; b. a first transistor having a first current-handling terminal coupled to the output terminal, a second current-handling terminal, and a first control terminal coupled to the input terminal to receive the input signal; c. a high-pass filter having a filter input node, coupled to the first control terminal, and a filter output node; d. a multiplexer having a first multiplexer input terminal coupled to the filter output node, a second multiplexer input terminal, and a multiplexer output terminal; e. a second transistor having a third current-handling terminal coupled to the first current-handling terminal, a fourth current-handling terminal, and a second control terminal coupled to the multiplexer output terminal; and f. a reference-voltage node coupled to the second multiplexer input terminal.
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18. A circuit for adjusting a received input signal having differential first and second signal halves, the circuit comprising:
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a. a first current-steering leg having; i. a first input node to receive the first signal half; ii. a first output node; iii. a first tail node; iv. first and second current-steering devices each having a first terminal coupled to the first input node, a second terminal coupled to the first output node, and a third terminal coupled to the first tail node; and v. a first filter; vi. wherein the first terminal of at least one of the first and second current-steering devices is coupled to the first input node via the first filter; b. a second current-steering leg having; i. a second input node to receive the second signal half; ii. a second output node; iii. a second tail node; iv. third and fourth current-steering devices each having fourth terminal coupled to the second input node, a fifth terminal coupled to the second output node, and a sixth terminal coupled to the second tail node; and v. a second filter; vi. wherein the fourth terminal of at least one of the third and fourth current-steering devices is coupled to the second input node via the second filter; and c. a regenerative load having a first load terminal coupled to the first output node and a second load terminal coupled to the second output node. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A circuit for adjusting a received input signal having differential first and second signal halves, the circuit comprising:
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a. a first current-steering leg having; i. a first input node to receive the first signal half; ii. a first output node; iii. a first tail node; iv. first and second current-steering devices each having a first terminal coupled to the first input node, a second terminal coupled to the first output node, and a third terminal coupled to the first tail node; and v. a first filter; vi. wherein the first terminal of at least one of the first and second current-steering devices is coupled to the first input node via the first filter; b. a second current-steering leg having; i. a second input node to receive the second signal half; ii. a second output node; iii. a second tail node; iv. third and fourth current-steering devices each having a fourth terminal coupled to the second input node, a fifth terminal coupled to the second output node, and a sixth terminal coupled to the second tail node; and v. a second filter; vi. wherein the fourth terminal of at least one of the third and fourth current-steering devices is coupled to the second input node via the second filter; c. a first switch coupled between the first filter and the first current-steering device and a second switch coupled between the second filter and the third current-steering device; and d. a regenerative load having a first load terminal coupled to the first output node and a second load terminal coupled to the second output node.
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25. A system for equalizing an input signal on a respective input terminal, the system comprising:
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a. a first transistor having a first current-handling terminal, a second current-handling terminal, and a first control terminal coupled to the input terminal; b. a second transistor having a third current-handling terminal coupled to the first current-handling terminal, a fourth current-handling terminal, and a second control terminal; c. a filter coupled between the input terminal and the second control terminal, the filter exhibiting a negative three (−
3) dB point;d. means for tuning the −
3 dB point; ande. means for selectively coupling the input terminal to the second control terminal via the filter.
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26. A differential receiver comprising:
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a. differential first and second input nodes to receive respective first and second differential signal components; b. differential first and second output nodes; c. a first leg including; i. a first transistor having a first current-handling terminal coupled to the first differential output node, a second current-handling terminal, and a first control terminal coupled to the first input node; ii. N second transistors, each having a third current-handling terminal coupled to the first differential output node, a fourth current-handling terminal, and a second control terminal; and iii. a first filter coupled between the first input node and at least one of the second control terminals of the N second transistors; d. a second leg including; i. a third transistor having a first current-handling terminal coupled to the second differential output node, a second current-handling terminal, and a first control terminal coupled to the second input node; ii. N fourth transistors, each having a third current-handling terminal coupled to the second differential output node, a fourth current-handling terminal, and a second control terminal; and iii. a second filter coupled between the second input node and at least one of the second control terminals of the N fourth transistors; e. a reference-voltage node; and f. a multiplexer selectively coupling the first control terminal of the first transistor to one of the reference-voltage node and the first input node. - View Dependent Claims (27, 28, 29, 30)
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31. A circuit comprising:
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a. first and second input nodes to receive respective first and second signal halves; b. first and second filters coupled to the respective first and second input nodes, the first filter to split the first input signal into a first signal portion and a filtered second signal portion, the second filter to split the second input signal into a third signal portion and a filtered fourth signal portion; c. first and second transistors to amplify the respective first and third signal portions and to provide the resulting amplified first and third signal portions on respective first and second output nodes; d. third and fourth transistors to amplify the respective filtered second and fourth signal portions and to provide the resulting amplified second and fourth signal portions on the respective first and second output nodes to combine with the respective amplified first and third signal portions; and e. N additional pairs of transistors, each of the additional transistors being coupled to one of the first and second output nodes. - View Dependent Claims (32, 33, 34)
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Specification