Power saving circuit employing visual persistence effect for backlight modules

• US 7,271,794 B1
• Filed: 10/05/2006
• Issued: 09/18/2007
• Est. Priority Date: 10/05/2006
• Status: Expired due to Fees

• Current Assignee: Zippy Technology Corporation
• Original Assignee: Zippy Technology Corporation
• Inventors: Chung, Chin-Biau, Cheng, Ying-Nan
• Primary Examiner(s): Philogene; Haissa
• Application Number:
  US11/543,138
• Time in Patent Office: 348 Days
• Field of Search: 315/294, 315/297, 315/307, 315/312, 315/360, 345/94, 345/102, 345/204, 345/212
• US Class Current: 345/102
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336

Abstract

A power saving circuit employing visual persistence effect for backlight modules aims to increase electric power at a duty mode to drive lighting units at a read end through driving units, and provide zero or lower electric power at a power saving mode to the lighting units at the rear end. Different lighting units generate light alternately in a first condition time sequence to enable user'"'"'s eyes to get images. In a second condition time sequence power consumption of the driving units is reduced and user'"'"'s eyes still can maintain visual sense of the images due to visual persistence effect, thereby electric power can be saved.

Claims

1. A power saving circuit employing visual persistence effect for backlight modules to drive alternately a plurality of lighting units located on a backlight module, comprising:

a time sequence generator to output a time sequence signal;

a logic circuit to receive the time sequence signal from the time sequence generator and generate a plurality of alternate cyclic signals that contain a first condition time sequence and a second condition time sequence; and

a plurality of driving units which have a duty mode and a power saving mode, each of the driving units receiving one alternate cyclic signal to drive one lighting unit and provide increased electric power for the lighting unit at a rear end at the duty mode in the first condition time sequence and provide zero or reduced electric power for the lighting unit at the rear end at the power saving mode in the second condition time sequence;

thereby the lighting unit generating light in the first condition time sequence to allow user'"'"'s eyes to get images, and power consumption of the driving unit in the second condition time sequence being reduced and the visual sense of the images in the user'"'"'s eyes still being maintained due to visual persistence effect thereby to save electric power.

2. The power saving circuit of claim 1, wherein the time sequence generator is a pulse width modulation controller.

3. The power saving circuit of claim 1, wherein the logic circuit is an inverter.

4. The power saving circuit of claim 1, wherein the time sequence signal has a frequency greater than one of 60 Hz, 120 Hz and 240 Hz.

5. The power saving circuit of claim 1, wherein each of the lighting units includes a plurality of lighting lamp sets.

6. The power saving circuit of claim 1, wherein the driving unit includes a pulse width modulation controller, a MOS switch and a ceramic piezoelectric plate to output electric power to the lighting units at the rear end.

7. The power saving circuit of claim 1, wherein the time sequence generator is electrically connected to a luminance control unit which generates a duty frequency to slice the driving electric power provided by the driving unit.

8. The power saving circuit of claim 7, wherein the luminance control unit is a pulse width modulation controller.

9. The power saving circuit of claim 1, wherein the first condition time sequence is high voltage condition time sequence, and the second condition time sequence is low voltage condition time sequence.

10. The power saving circuit of claim 1, wherein the first condition time sequence is high voltage condition time sequence, and the second condition time sequence is zero voltage condition time sequence.