Priority circuit for content addressable memory
First Claim
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1. A digital signal processor, comprising:
- a content addressable memory (CAM) array having a plurality of rows of CAM cells;
an array of storage elements having a plurality of rows of the storage elements coupled to the CAM array, each row of storage elements to store a number corresponding to a data word stored in one of the rows of the CAM cells; and
priority logic coupled to the array of storage elements, the priority logic to provide to a plurality of priority signal lines an indication of a location of a particular number in the array of storage elements, wherein the priority logic comprises;
a first plurality of compare circuits, each compare circuit coupled to one of the storage elements in the array of storage elements, and each compare circuit having a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the plurality of priority signal lines; and
a delay circuit coupled to each of the first plurality of compare circuits.
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Abstract
A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.
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Citations
19 Claims
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1. A digital signal processor, comprising:
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a content addressable memory (CAM) array having a plurality of rows of CAM cells; an array of storage elements having a plurality of rows of the storage elements coupled to the CAM array, each row of storage elements to store a number corresponding to a data word stored in one of the rows of the CAM cells; and priority logic coupled to the array of storage elements, the priority logic to provide to a plurality of priority signal lines an indication of a location of a particular number in the array of storage elements, wherein the priority logic comprises; a first plurality of compare circuits, each compare circuit coupled to one of the storage elements in the array of storage elements, and each compare circuit having a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the plurality of priority signal lines; and a delay circuit coupled to each of the first plurality of compare circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of operating a digital signal processor, comprising:
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outputting a first priority number signal on a priority line coupled to a first column of compare circuits, the first priority number signal having one of at least two logical signal levels based, at least in part, on a comparison of priority number bits stored within a first column of priority number storage elements coupled to the first column of compare circuits; and concurrently de-asserting a match line in the first column of compare circuits and outputting a second priority number signal on a next priority line coupled to a second column of compare circuits, the second priority number signal having one of the at least two logical signal levels based, in part, on a comparison of priority number bits stored within a second column of priority number storage elements coupled to the second column of compare circuits. - View Dependent Claims (17, 19)
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18. A digital signal processor, comprising:
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means for outputting a first priority number signal on a priority line coupled to a first column of compare circuits, the first priority number signal having one of at least two logical signal levels based, at least in part, on a comparison of priority number bits stored within a first column of priority number storage elements coupled to the first column of compare circuits; and means for concurrently de-asserting a match line in the first column of compare circuits and outputting a second priority number signal on a next priority line coupled to a second column of compare circuits, the second priority number signal having one of the at least two logical signal levels based, in part, on a comparison of priority number bits stored within a second column of priority number storage elements coupled to the second column of compare circuits.
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Specification