Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells

• US 7,272,035 B1
• Filed: 08/31/2005
• Issued: 09/18/2007
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Chen, Eugene Youjun, Huai, Yiming
• Primary Examiner(s): Ho; Hoai V.
• Application Number:
  US11/217,524
• Time in Patent Office: 748 Days
• Field of Search: 365/158, 365/207, 365/209, 365/210
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each of the plurality of magnetic storage cells includes a magnetic element and a selection transistor. The magnetic element may be programmed using spin transfer induced switching by a write current driven through the magnetic element. The selection transistor includes a source and a drain. The plurality of magnetic storage cells are grouped in pairs. The source of the selection transistor for one magnetic storage cell of a pair shares the source with the selection transistor for another magnetic storage cell of the pair.

Claims

1. A magnetic memory comprising:

a plurality of magnetic storage cells, each of the plurality of magnetic storage cells including a magnetic element and a selection transistor, the magnetic element capable of being programmed using spin transfer induced switching by a write current driven through the magnetic element, the selection transistor including a source and a drain, the plurality of magnetic storage cells being grouped in pairs, the source of the selection transistor for one magnetic storage cell of a pair sharing the source with the selection transistor for another magnetic storage cell of the pair, the selection transistor configured such that the write current is driven through the magnetic element during the writing of the magnetic element;

a plurality of bit lines coupled with the plurality of magnetic storage cells and for carrying the write current or the read current, a portion of the plurality of bit lines being held at a particular voltage when selected; and

a plurality of bit line selectors coupled with the bit lines, the plurality of bit line selectors configured to activate a portion of the plurality of bit line to provide the write current in a desired direction to each of the plurality of magnetic storage cells; and

a plurality of source lines coupled with the plurality of magnetic storage cells and carrying an additional voltage when activated, the additional voltage having a value smaller or larger than the particular voltage to provide the write current in a desired direction; and

a plurality of source line selectors coupled with the plurality of source lines and for activating a portion of the plurality of source lines.

2. The magnetic memory of claim 1 further comprising:

a plurality of reference cells;

at least one differential sensor coupled with the plurality of magnetic storage cells and the plurality of reference cells; and

at least one comparator coupled with the at least one differential sensor.

3. The magnetic memory of claim 2 wherein each of the at least one differential sensor includes at least one differential current sensor.

4. The magnetic memory of claim 1 further comprising:

error correction circuitry coupled with the plurality of magnetic storage cells.

5. The magnetic memory of claim 1 wherein the selection transistor is configured such that the write current is substantially a maximum allowable current for the transistor regardless of a state of the at least one magnetic element being written.

6. The magnetic memory of claim 5 wherein the selection transistor is configured to maintain a maximum rated gate-source voltage and a drain-source voltage that is not less than a gate-source voltage minus a transistor threshold voltage.

7. The magnetic memory of claim 5 further comprising:

at least one of at least one charge pump and at least one voltage splitter coupled with the selection transistor and the magnetic element, thereby providing at least one positive voltages higher than a supply voltage at a particular portion of the selection transistor and the magnetic element.

8. The magnetic memory of claim 5 further comprising:

at least one of at least one charge pump and at least one voltage splitter coupled with the selection transistor and the magnetic element, thereby providing at least one negative voltage lower than ground voltage.

9. The magnetic memory of claim 1 wherein the magnetic element has a lateral dimension of not more than one hundred sixty nanometers.

10. The magnetic memory of claim 1 wherein each of the plurality of magnetic storage cells has an area and wherein the magnetic element has a lateral dimension, the area being not more than sixteen times the square of the lateral dimension.

11. The magnetic memory of claim 1 wherein each of the plurality of magnetic storage cells is configured such that the write current is a symmetric write current.