Non-volatile memory device and erase method of the same

• US 7,272,050 B2
• Filed: 02/17/2005
• Issued: 09/18/2007
• Est. Priority Date: 08/10/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Eui-Gyu, Han, Gyeong-Soo, Kim, Kil-Yeon
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Le; Toan
• Application Number:
  US11/060,915
• Publication Number:
  US 20060034128A1
• Time in Patent Office: 943 Days
• Field of Search: 365/185.22, 365/185.29, 365/185.24, 365/185.27
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

Claims

1. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:

erasing the memory cells at the same time; and

performing an erase-verify operation for the erased memory cells, wherein the erase-verify operation is repeated under different bias conditions of the rows, wherein the erase-verify operation includes a first erase-verify operation and a second erase-verify operation which are sequentially performed, and wherein the first erase-verify operation is performed under a first bias condition in which a first read voltage is applied to a first part of the rows and a second read voltage is applied to another part of the rows.

2. The erase method as recited in claim 1, wherein the second erase-verify operation is performed under a second bias condition in which the second read voltage is applied to the first part of the rows and the first read voltage is applied to the another part of the rows.

3. The erase method as recited in claim 1, wherein the first read voltage is approximately 0V and the second read voltage is approximately 5V.

4. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:

erasing the memory cells at the same time; and

performing an erase-verify operation for the erased memory cells, wherein the erase-verify operation is repeated under different bias conditions of the rows, wherein the erase-verify operation includes a first erase-verify operation and a second erase-verify operation which are sequentially performed,

wherein the erasing the memory cells and the performing an erase-verify operation are repeated within a number of predetermined erase cycles according to results of the first and the second erase-verify operation.

5. The erase method as recited in claim 4, wherein a combination of the results of the first and the second erase-verify operations is stored as a value in a status register of the non-volatile memory device.

6. The erase method as recited in claim 5, wherein the value is output externally by a state read operation.

7. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:

erasing the memory cells at the same time; and

performing an erase-verify operation for the erased memory cells, wherein the erase-verify operation is repeated under different bias conditions of the rows,

wherein the non-volatile memory device is a NAND flash memory device.

8. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being serially coupled between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:

erasing the memory cells at the same time;

performing a first erase-verify operation while a first read voltage is applied to a part of the wordlines and a second read voltage higher than the first read voltage is applied to another part of the wordlines; and

performing a second erase-verify operation while the second read voltage is applied to the part of the wordlines and the first read voltage is applied to the another part of the wordlines.

9. The erase method as recited in claim 8, wherein the first read voltage is approximately 0V and the second read voltage is approximately 5V.

10. The erase method as recited in claim 8, wherein the erasing the memory cells, performing a first erase-verify operation, and the performing a second erase-verify operation are repeated within a number of predetermined erase cycles according to results of the first and the second erase-verify operation.

11. The erase method as recited in claim 10, wherein a combination of the results of the first and the second erase-verify operations is stored as a value in a status register of the non-volatile memory device.

12. The erase method as recited in claim 11, wherein the value is output externally by a state read operation.

13. The erase method as recited in claim 8, wherein the second read voltage is applied to the string select line and the ground select line in the performing a first erase-verify operation, and the performing a second erase-verify operation.

14. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being serially coupled between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:

performing a first erase-verify operation while a first read voltage is applied to first ones of the wordlines and a second read voltage higher than the first read voltage is applied to second ones of the wordlines;

performing a second erase-verify operation while the second read voltage is applied to the first ones of the wordlines and the first read voltage is applied to the second ones of the wordlines; and

judging an erase operation of the memory cells according to results of the first and the second erase-verify operations.

15. The erase method as recited in claim 14, wherein the first read voltage is approximately 0V and the second read voltage is approximately 5V.

16. The erase method as recited in claim 14, wherein the performing a first erase-verify operation, the performing a second erase-verify operation, and the judging an erase operation are repeated within a number of predetermined erase cycles according to results of the first and the second erase-verify operation.

17. The erase method as recited in claim 16, wherein a combination of the results of the first and the second erase-verify operations is stored as a value in a status register of the non-volatile memory device.

18. The erase method as recited in claim 17, wherein the value is output externally by a state read operation.

19. The erase method as recited in claim 14, wherein the second read voltage is applied to the string select line and the ground select line in the performing a second erase-verify operation, and the judging an erase operation.

20. A non-volatile memory device comprising:

a string select line connected to a string select transistor;

a ground select line connected to a ground select transistor;

wordlines connected to memory cells and divided into at least two groups;

a row decoder circuit configured to control the wordlines and the string select line and the ground select line; and

an erase controller to control the row decoder circuit so that the wordlines of a first group of the wordlines are set to a different bias condition than the wordlines of a second group of the wordlines, in respective first and second erase-verify operations.

21. The non-volatile memory device as recited in claim 20, wherein the first erase-verify operation is performed under a first bias condition in which a first read voltage is applied to the wordlines of the first group of the wordlines and a second read voltage is applied to the wordlines of the second group of the wordlines.

22. The non-volatile memory device as recited in claim 21, wherein the second erase-verify operation is performed under a second bias condition in which the second read voltage is applied to the wordlines of the first group of the wordlines and the first read voltage is applied to the wordlines of the second group of the wordlines.

23. The non-volatile memory device as recited in claim 22, wherein the first read voltage is approximately 0V and the second read voltage is approximately 5V.

24. The non-volatile memory device as recited in claim 22, wherein the erase controller includes a status register in which a combination of results of the first and the second erase-verify operation is stored as a value.

25. The non-volatile memory device as recited in claim 24, wherein the value is output externally by a state read operation.

26. The non-volatile memory device as recited in claim 21, wherein the second read voltage is applied to the string select line and the ground select line in the first and the second erase-verify operations.

27. An erase method of a non-volatile memory device including a plurality of cell strings each having a first select transistor connected to a string select line, a second select transistor connected to a ground select line, and memory cells being connected in series between the first and the second select transistors, and each being connected to corresponding wordlines, the erase method comprising:

applying a first voltage to a gate of the first select transistor;

applying the first voltage to a gate of the second select transistor;

supplying a sensing current to a drain of the first select transistor; and

applying a second voltage higher than 0V to respective control gates of the memory cells.

28. The erase method as recited in claim 27, wherein the first voltage is approximately 5V.

29. The erase method as recited in claim 27, wherein the second voltage is approximately 0.2V˜

0.3V.

30. An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns, the erase method comprising:

erasing the memory cells at the same time; and

performing an erase-verify operation for the erased memory cells,

wherein a higher voltage than 0V is applied to each of the rows during the erase-verify operation.

31. The erase method as recited in claim 30, wherein a voltage supplied to the rows is approximately 0.2V˜

0.3V.