Method of transferring data between computer peripherals

• US 7,272,680 B2
• Filed: 03/09/2005
• Issued: 09/18/2007
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kuo, Chien-Cheng
• Primary Examiner(s): Ray; Gopal C.
• Application Number:
  US11/074,627
• Publication Number:
  US 20060129734A1
• Time in Patent Office: 923 Days
• Field of Search: 710/308, 710/72, 710 20- 22, 710/1, 710/3, 710/33, 710/52, 370/400, 370/389, 370/351, 370/252, 370/464, 370/912, 709/212, 709/250, 709/219, 709/201, 709/232, 709/238, 709/253, 340/825.52
• US Class Current: 710/308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.

Claims

1. A method for accessing data, comprising the step of:

transferring data registered by a first host controller to a second host controller directly,

wherein the transferring further comprises an initialize state, a programming state, and a transfer state, and wherein the CPU is being used to program an operational register of the first host controller for setting the data length, data type, begin/end address, and state of the first host controller while there are data required to be transferred from the first host controller to the second host controller as the transferring is in the programming state.

2. The method of claim 1 wherein the first host controller is initialized by way of using a central processing unit (CPU) to program one of a plurality of operational registers of the first host controller to ensure a normal operation of the first host controller while the transferring is in the initialize state.

3. The method of claim 1 wherein the normal operation of the first host controller includes activating the first host controller, suspending/resuming the working of the first host controller and disabling part of the function of the first host controller.

4. The method of claim 1, wherein the first host controller sets a transfer status thereof corresponding to the second host controller with respect to the setting of the operational register.

5. The method of claim 1, wherein the CPU issues a master cycle of a direct memory access (DMA) function to the operational register for programming the DMA function.

6. A method for accessing data, comprising the step of:

transferring data registered by a first host controller to a second host controller directly,

wherein the transferring further comprises an initialize state, a programming state, and a transfer state, and wherein the transferring of data between the first host controller and the second host controller as the transferring is in the transfer state can be accomplished according to four cases addressed as following a case of single master write, a case of single master read, a case of two master write and a case of two master read.

7. The method of claim 6, further comprising the step of:

enabling the DMA function of the first host controller and issuing a master cycle by the first host controller to read and confirm a transfer status of the second host controller for making an evaluation to determine whether the first host controller is able to actively transfer data to the second host controller, while the transferring of data from the first host controller to the second host controller as the transferring is in the transfer state is being accomplished by the case of single master write.

8. The method of claim 7, wherein the transfer status of the second host controller includes buffer size of a transfer data buffer of the second host controller, status of the transfer data buffer, and buffer begin address of the transfer data buffer.

9. The method of claim 7, further comprising the steps of:

using the first host controller to transfer the data obtained from a corresponding first external bus to the transfer data buffer of the second host controller while the transfer status of the second host controller is defined as ready;

moving data from the transfer data buffer of the second host controller to a second external bus corresponding to the second host controller for completing the data transferring after the data is being received by the second host controller; and

updating the transfer status of the first host controller and the transfer status of the second host controller automatically while the transfer status of the second host controller can be updated according to the setting of the operational register of the first host controller, after the data transferring is completed.

10. The method of claim 7, further comprising the step of:

controlling by the first host controller for selectively adapting a plurality of master write cycles for separating the data into a plurality of corresponding packets and moving the same form the first host controller to the second host controller separately while the total data length is larger than the buffer size of the transfer data buffer of the second host controller.

11. The method of claim 10, wherein the data is being continuously transferred from the first host controller to the second host controller while a next data to be transferred is ready on the first external bus corresponding to the first host controller.

12. The method of claim 7, further comprising the step of:

issuing a master cycle by the first host controller to read and confirm the transfer status of the second host controller again while the transfer status of the transfer data buffer of the second host controller is defined as not ready.

13. The method of claim 6, further comprising the step of:

enabling the DMA function of the second host controller and issuing a master cycle by the second host controller to read and confirm a transfer status of the first host controller for making an evaluation to determine whether the second host controller is able to actively access data from the first host controller, while the transferring of data from the first host controller to the second host controller as the transferring is in the transfer state is being accomplished by the case of single master read.

14. The method of claim 13, further comprising the steps of:

accessing the registered data of the first host controller by the second host controller while the transfer status of the first host controller is defined as ready and the buffer size of the transfer data buffer of the second host controller is larger than total data length; and

controlling by the second host controller for selectively adapting a plurality of master write cycles for separating the data into a plurality of corresponding packets and accessing the data from the first host controller separately while the total data length is larger than the buffer size of the transfer data buffer of the second host controller.

15. The method of claim 13, further comprising the steps of:

issuing a master cycle by the second host controller to read and confirm the transfer status of the first host controller again while the transfer status of the first host controller is defined as not ready; and

updating the transfer status of the first host controller and the transfer status of the second host controller automatically while the transfer status of the first host controller can be updated according to the setting of the operational register of the second host controller, after the data accessing is completed.

16. The method of claim 6, further comprising the step of:

enabling both the DMA function of the first and the second host controllers simultaneously and issuing a master cycle by the second host controller to inform the first host controller of its transfer status for making an evaluation to determine whether the first host controller is able to actively transfer data to the second host controller, while the transferring of data from the first host controller to the second host controller as the transferring is in the transfer state is being accomplished by the case of two master write.

17. The method of claim 6, further comprising the step of:

enabling both the DMA function of the first and the second host controllers simultaneously and issuing a master cycle by the first host controller to inform the second host controller of its transfer status for making an evaluation to determine whether the second host controller is able to actively access data from the first host controller, while the transferring of data from the first host controller to the second host controller as the transferring is in the transfer state is being accomplished by the case of two master read.

18. The method of claim 6, further comprising the step of:

enabling both the DMA function of the first and the second host controllers simultaneously and performing an operation selected from the group consisting of accessing data actively by the destination thereof from the origin thereof and transferring data actively by the origin thereof to the destination thereof, while the transferring of data is being performed between the first host controller and the second host controller and is being accomplished by a case of mixing read and write.

19. The method of claim 6, wherein the first host controller is initialized by way of using a central processing unit (CPU) to program one of a plurality of operational registers of the first host controller to ensure a normal operation of the first host controller while the transferring is in the initialize state.

20. The method of claim 6, wherein the normal operation of the first host controller includes activating the first host controller, suspending/resuming the working of the first host controller and disabling part of the function of the first host controller.