Exploitive test pattern apparatus and method

• US 7,272,756 B2
• Filed: 05/03/2005
• Issued: 09/18/2007
• Est. Priority Date: 05/03/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Smith, Lane A., Olsen, Max J., Schiessler, Gary E., Brink, Robert D., Hofmann, James Walter Jr.
• Primary Examiner(s): Britt; Cynthia
• Assistant Examiner(s): Trimmings; John P
• Application Number:
  US11/121,152
• Publication Number:
  US 20060253748A1
• Time in Patent Office: 868 Days
• Field of Search: None
• US Class Current: 714/715
• CPC Class Codes: H04L 1/244 test sequence generators
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.

Claims

1. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bits; and

generating a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern; and

n is greater than m such that said test consecutive identical digit portion is longer than said baseline consecutive identical digit portion, and such that bit locking ability of said communications equipment may be subjected to a more rigorous test condition via said modified test pattern as compared to said baseline test pattern.

2. The method of claim 1 wherein:

m=72;

p≧

10328; and

said baseline PRBS comprises a standard PRBS31 corresponding to output that would be obtained from a thirty-one-stage shift register having twenty-eighth and thirty-first stage outputs added in a modulo-two addition stage with a result of said addition being fed back to a first-stage input.

3. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bit; and

generating a test pseudo random bit sequence portion comprising g bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern;

said baseline pseudo random bit sequence and said test pseudo random bit sequence are identical, and

q is less than p, such that said test pseudo random bit sequence portion is truncated with respect to said baseline pseudo random bit sequence portion, and such that said modified test pattern provides a higher frequency toggle rate as compared to said baseline test pattern.

4. The method of claim 3 wherein:

m=72;

p≧

10328; and

said baseline PRBS comprises a standard PRBS31 corresponding to output that would be obtained from a thirty-one-stage shift register having twenty-eighth and thirty-first stage outputs added in a modulo-two addition stage with a result of said addition being fed back to a first-stage input.

5. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bits; and

generating a test pseudo random bit sequence portion comprising bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern;

said baseline pseudo random bit sequence and said test pseudo random bit sequence are identical, and

wherein q is greater than p, such that said test pseudo random bit sequence portion is stretched with respect to said baseline pseudo random bit sequence portion, and such that said modified test pattern provides a more realistic test, as compared to said baseline test pattern, for conditions wherein long data frames are employed.

6. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bits; and

generating a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern; and

said test pseudo random bit sequence comprises a lower order polynomial function than said baseline pseudo random bit sequence, such that said modified test pattern provides a higher frequency toggle rate as compared to said baseline test pattern.

7. The method of claim 6, wherein:

m=72;

p≧

10328; and

said baseline pseudo random bit sequence comprises a standard PRBS31 corresponding to output that would be obtained from a thirty-one-stage shift register having twenty-eighth and thirty-first stage outputs added in a modulo-two addition stage with a result of said addition being fed back to a first-stage input.

8. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern o having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bits; and

generating a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern; and

said test pseudo random bit sequence comprises a higher order polynomial function than said baseline pseudo random bit sequence, such that said modified test pattern provides a more realistic test, as compared to said baseline test pattern, for conditions wherein long data frames are employed.

9. A method of generating a modified test pattern for testing communications equipment, said pattern being modified with respect to a baseline pattern having a baseline consecutive identical digit consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said method comprising the steps of:

generating a test consecutive identical digit portion comprising n consecutive identical bits;

generating a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein;

at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern; and

said baseline pattern comprises multiple repetitions of said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, said p bits being identical for each repetition and resulting from a re-seeding of said baseline pseudo random bit sequence; and

repeating said steps of generating said test consecutive identical digit portion and generating said test pseudo random bit sequence portion, said step of said generation of said test pseudo random bit sequence portion being repeated without re-seeding said test pseudo random bit sequence, such that randomness is effectively introduced into a length of said test consecutive identical digit portion.

10. The method of claim 9 wherein:

m=72;

p≧

10328; and

said baseline pseudo random bit sequence comprises a standard PRBS31 corresponding to output that would be obtained from a thirty-one-stage shift register having twenty-eighth and thirty-first stage outputs added in a modulo-two addition stage with a result of said addition being fed back to a first-stage input.

11. An apparatus for testing a communications device with a test pattern that is modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said apparatus comprising:

a pattern generator that is configured to;

generate a test consecutive identical digit portion comprising n consecutive identical bits; and

generate a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern;

a checker that is configured to measure performance of the communications device when exposed to said test pattern generated by said pattern generator; and

an interface module that is configured to couple the communications device to said pattern generator and said checker;

wherein said baseline pattern comprises multiple repetitions of said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, said p bits being identical for each repetition and resulting from a re-seeding of said baseline pseudo random bit sequence, said pattern generator being further configured to repeat said generating of said test consecutive identical digit portion and said generating of said test pseudo random bit sequence portion, said generation of said test pseudo random bit sequence portion being repeated without re-seeding said test pseudo random bit sequence, such that randomness is effectively introduced into a length of said test consecutive identical digit portion.

12. An integrated circuit for communications applications, with built-in test capability using a test pattern that is modified with respect to a baseline pattern having a baseline consecutive identical digit portion with m consecutive identical bits and a baseline pseudo random bit sequence portion with p bits of a baseline pseudo random bit sequence, said integrated circuit comprising:

a communications portion; and

a built-in test portion, said built-in test portion in turn comprising;

a pattern generator that is configured to;

generate a test consecutive identical digit portion comprising n consecutive identical bits; and

generate a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein at least one of said test consecutive identical digit portion and said test pseudo random bit sequence portion is modified with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, respectively, said modification being performed to enhance diagnostic value of said modified test pattern with respect to said baseline pattern;

a checker that is configured to measure performance of said communications portion when exposed to said test pattern generated by said pattern generator; and

an interface portion that couples said communications portion to said pattern generator and said checker;

wherein said baseline pattern comprises multiple repetitions of said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, said p bits being identical for each repetition and resulting from a re-seeding of said baseline pseudo random bit sequence, said pattern generator being further configured to repeat said generating of said test consecutive identical digit portion and said generating of said test pseudo random bit sequence portion, said generation of said test pseudo random bit sequence portion being repeated without re-seeding said rest pseudo random bit sequence, such that randomness is effectively introduced into a length of said test consecutive identical digit portion.

13. A data structure embodied in a computer readable medium, the data structure used to test a device, the data structure comprising:

a test consecutive identical digit portion comprising n consecutive identical bits; and

a test pseudo random bit sequence portion comprising q bits of a test pseudo random bit sequence;

wherein at least one of;

(i) said test consecutive identical digit portion, and

(ii) said test pseudo random bit sequence portion is modified with respect to a baseline pattern having;

(i) a baseline consecutive identical digit portion comprising 72 consecutive identical bits, and

(ii) a baseline pseudo random bit sequence portion comprising at least 10328 bits of a standard PRBS31 corresponding to output that would be obtained from a thirty-one-stage shift register having twenty-eighth and thirty-first stage outputs added in a modulo-two addition stage with a result of said addition being fed back to a first-stage input, respectively,

said modification being performed to enhance diagnostic value of said data structure with respect to said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion;

wherein said baseline pattern comprises multiple repetitions of said baseline consecutive identical digit portion and said baseline pseudo random bit sequence portion, said bits of said baseline pseudo random bit sequence portion being identical for each repetition and resulting from a re-seeding of said baseline pseudo random bit sequence, said test pseudo random bit sequence portion being repeated in said data structure without re-seeding said test pseudo random bit sequence, such that randomness is effectively introduced into a length of said test consecutive identical digit portion.

14. The data structure of claim 13 where said modification is performed to enhance said diagnostic value with respect to synchronous optical network applications.

15. The data structure of claim 13 where said modification is performed to enhance said diagnostic value with respect to Fibre Channel applications.