Coarse tuning for fractional-N synthesizers

• US 7,274,229 B1
• Filed: 06/22/2006
• Issued: 09/25/2007
• Est. Priority Date: 05/11/2004
• Status: Expired due to Fees

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Bunch, Ryan, Humphreys, Scott
• Primary Examiner(s): Wells; Kenneth B.
• Assistant Examiner(s): Luu; An T.
• Application Number:
  US11/472,889
• Time in Patent Office: 460 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/193 the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

Claims

1. A fractional-N frequency synthesizer comprising:

a phase lock look (PLL);

coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation;

wherein the coarse tuning circuitry comprises divide value generation circuitry adapted to;

provide an integer divide value to a divider of the PLL when operating in the integer division mode; and

provide a fractional sequence of divide values to the divider of the PLL when operating in the fractional-N division mode,

wherein the integer divide value includes an integer component of a product of a desired N value and a modulus M.

2. A fractional-N frequency synthesizer comprising:

a phase lock loop (PLL);

coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation;

wherein the coarse tuning circuitry comprises divide value generation circuitry adapted to;

provide an integer divide value to a divider of the PLL when operating in the integer division mode; and

provide a fractional sequence of divide values to the divider of the PLL when operating in the fractional-N division mode,

wherein the fractional sequence of divide values includes a sum of an integer and a sequence of integer values having an average value equal to a desired fraction.

3. The fractional-N frequency synthesizer of claim 2 wherein the coarse tuning circuitry comprises decision circuitry, wherein the decision circuitry is adapted to select an integer divide value in order to place the PLL in integer division mode and to select a fractional sequence of divide values in order to place the PLL in fractional-N division mode.

4. The fractional-N frequency synthesizer of claim 3 wherein the decision circuitry includes a multiplexer.

5. A fractional-N frequency synthesizer comprising:

a phase lock loop (PLL);

coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation,

wherein the coarse tuning circuitry comprises decision circuitry wherein the decision circuitry is adapted to select an integer divide value in order to place the PLL in integer division mode and to select a fractional sequence of divide values in order to place the PLL in fractional-N division mode, and

wherein the coarse tuning circuitry is adapted to select first and second values for a loop control signal and wherein the decision circuitry is adapted to;

select the integer divide value in order to place the PLL in integer division mode in response to the loop control signal having the first value; and

select the fractional sequence of divide values in order to place the PLL in fractional-N division mode in response to the loop control signal having the second value.

6. A method for coarse tuning a fractional-N frequency synthesizer comprising:

controlling a phase lock loop (PLL) such that the PLL operates in an integer division mode during coarse tuning; and

controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation,

wherein controlling the PLL such that the PLL operates in the integer division mode during coarse tuning includes controlling a decision circuit such that an integer divide value is provided to a divider of the PLL during coarse tuning and wherein controlling the PLL such that the PLL operates in the fractional-N division mode during normal operation includes controlling the decision circuit such that a fractional sequence of divide values is provided to the divider of the PLL during normal operation, and wherein the integer divide value includes an integer component of a product of a desired N value and a modulus M.

7. The method of claim 6 wherein the fractional sequence of divide values includes a sum of an integer and a sequence of integer values having an average value equal to a desired fraction.

8. A method for coarse tuning a fractional-N frequency synthesizer comprising:

controlling a phase lock loop (PLL) such that the PLL operates in an integer division mode during coarse tuning; and

controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation,

selecting a first value for a loop control signal wherein controlling the decision circuit such that the decision circuit outputs the integer divide value during coarse tuning is performed in response to selecting the first value for the loop control signal; and

selecting a second value for the loop control signal wherein controlling the decision circuit such that the decision circuit outputs the integer divide value during coarse tuning is performed in response to selecting the second value for the loop control signal,

wherein controlling the PLL such that the PLL operates in the integer division mode during coarse tuning includes controlling a decision circuit such that an integer divide value is provided to a divider of the PLL during coarse tuning and wherein controlling the PLL such that the PLL operates in the fractional-N division mode during normal operation includes controlling the decision circuit such that a fractional sequence of divide values is provided to the divider of the PLL during normal operation.

9. A method for coarse tuning a fractional-N frequency synthesizer comprising:

providing an integer divide value to a divider of a phase lock loop (PLL) during coarse tuning, thereby controlling the PLL such that the PLL operates in an integer division mode during coarse tuning; and

providing a fractional sequence of divide values to the divider of the PLL during normal operation, thereby controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation,

wherein controlling the PLL such that the PLL operates in the integer division mode during coarse tuning includes selectively coupling the integer divide value to the PLL and wherein controlling the PLL such that the PLL operates in the fractional-N division mode during normal operation includes selectively coupling the fractional sequence of divide values to the PLL, and

wherein selectively coupling the integer divide value to the PLL includes multiplexing the integer divide value to the PLL in response to a first value for a loop filter control signal and wherein selectively coupling the fractional sequence of divide values to the PLL includes multiplexing the fractional sequence of divide values to the PLL in response to a second value for the loop filter control signal.