Random access memory with stability enhancement and early read elimination
First Claim
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1. A random access memory, comprising:
- a memory cell including at least one access device, the at least one access device being switched on or off in accordance with a signal on a wordline to conduct a memory operation through the at least one access device, the at least one access device configured to gate a bitline signal; and
a logic circuit coupled to the wordline to receive and gate the wordline signal in accordance with an enable signal at the logic circuit, wherein the enable signal ensures that an arrival of the bitline signal at the at least one access device occurs at or before the arrival of the signal on the wordline.
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Abstract
A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.
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Citations
14 Claims
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1. A random access memory, comprising:
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a memory cell including at least one access device, the at least one access device being switched on or off in accordance with a signal on a wordline to conduct a memory operation through the at least one access device, the at least one access device configured to gate a bitline signal; and a logic circuit coupled to the wordline to receive and gate the wordline signal in accordance with an enable signal at the logic circuit, wherein the enable signal ensures that an arrival of the bitline signal at the at least one access device occurs at or before the arrival of the signal on the wordline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A static random access memory, comprising:
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a memory cell including first and second access transistors respectively coupled to first and second bitlines, the first and second access transistors having gates coupled to a connection node; and a logic circuit coupled to a wordline, the logic circuit selectively coupling the wordline to the connection node in accordance with an enable signal, wherein the enable signal provides for an arrival of the bitline signal at or before a trigger signal of the wordline such that the trigger signal on the wordline is synchronized with bit line signals to ensure an arrival of the bit line signals at or before the trigger signal to reduce or eliminate an early read condition. - View Dependent Claims (10, 11, 12, 13, 14)
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Specification