Bitline exclusion in verification operation
First Claim
Patent Images
1. A method of performing operations on a bitline in a memory device, comprising:
- setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and
excluding the bitline from operations when a program latch for the bitline fails to program.
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Accused Products
Abstract
Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.
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Citations
40 Claims
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1. A method of performing operations on a bitline in a memory device, comprising:
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setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and excluding the bitline from operations when a program latch for the bitline fails to program. - View Dependent Claims (2)
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3. A method of performing operations on a bitline in a memory device, comprising:
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setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and disabling the bitline for verification operation, wherein disabling the bitline for verification operation comprises pulling a verification node to ground.
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4. A method of determining whether a programming operation on a bitline in a memory has failed, comprising:
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loading a bitline disable latch with a first logic level signal; loading a program latch with a second logic level signal complementary to the first logic level signal; attempting to program a bit; determining whether the bit has programmed; and indicating a failed programming when the bit exhibits an erase threshold voltage. - View Dependent Claims (5, 6)
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7. A method of monitoring programming and verification on a bitline in a memory, comprising:
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inhibiting operation of a program latch when a bitline is excluded from operation; inhibiting operation of the program latch when a bitline is available for operations and the bitline fails a programming operation; and indicating a failure of programming when the bitline fails the programming operation. - View Dependent Claims (8, 9)
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10. A method of monitoring each of a plurality of bitlines in a memory for failed programming operation, comprising:
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connecting a plurality of bitline disable circuits, each bitline disable circuit connected to a single bitline of the bitlines in the memory, to a common node; precharging the common node; discharging the common node when any of the plurality of bitline disable circuits indicate a failed programming operation.
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11. A method of verifying programming on a bitline in a memory, comprising:
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precharging a common node for the memory; checking for a failed program operation on any of a plurality of programming latches in the memory; discharging the common node when any of the plurality of program latches fails to program; and asserting a fail signal in response to the discharge of the common node. - View Dependent Claims (12)
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13. A method of programming a bit on a bitline, comprising:
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loading a bitline disable latch with a first logic signal indicating a valid operational bitline; loading a program latch with a complement to the first logic signal; conditioning a bitline; and initiating a program operation on the bitline. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A memory device, comprising:
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an array of memory cells; control circuitry to read, write and erase the memory cells; address circuitry to latch address signals provided on address input connections; and a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising; a program latch to initiate programming of the memory; and a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated. - View Dependent Claims (21, 22, 23, 24, 25)
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26. A non-volatile memory device, comprising:
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an array of floating gate memory cells; control circuitry to read, write and erase the floating gate memory cells; and address circuitry to latch address signals provided on address input connections; a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory; and a program verify circuit comprising; first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground. - View Dependent Claims (27, 28)
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29. An integrated circuit, comprising:
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a bitline disable circuit comprising; a bitline disable latch having an input and an output; a program latch having an input and an output; and a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential; a program verify circuit comprising; second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and a read/verify sense circuit comprising; a sense precharge transistor source to drain connected between a supply voltage and a sense node; a bitline sense transistor source to drain connected between the sense node and a bitline; and a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing when a sensed bit on the bitline is programmed.
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30. A bitline disable circuit, comprising:
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a bitline disable latch having an input and an output; a program latch having an input and an output; and a transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and ground.
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31. A program verify circuit, comprising:
first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal.
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32. A read/verify sense circuit, comprising:
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a sense precharge transistor source to drain connected between a supply voltage and a sense node; a bitline sense transistor source to drain connected between the sense node and a bitline; and a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.
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33. A processing system, comprising:
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a processor; and a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising; an array of memory cells; control circuitry to read, write and erase the memory cells; address circuitry to latch address signals provided on address input connections; and a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising; a program latch to initiate programming of the memory; a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated. - View Dependent Claims (34, 35, 36, 37)
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38. A flash memory device, comprising:
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an array of floating gate memory cells; control circuitry to read, write and erase the floating gate memory cells; and address circuitry to latch address signals provided on address input connections; and a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising; a program latch to initiate programming of the memory; a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated. - View Dependent Claims (39, 40)
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Specification