Bitline exclusion in verification operation

• US 7,274,607 B2
• Filed: 06/15/2005
• Issued: 09/25/2007
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Louie, Benjamin, Yip, Aaron, Hartono, Hendrik
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US11/153,188
• Publication Number:
  US 20060285390A1
• Time in Patent Office: 832 Days
• Field of Search: 365/195
• US Class Current: 365/195
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements

Abstract

Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines is excluded or if a programming operation fails.

Claims

1. A method of performing operations on a bitline in a memory device, comprising:

setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and

excluding the bitline from operations when a program latch for the bitline fails to program.

2. The method of claim 1, wherein excluding the bitline from operations when a program latch fails to program comprises:

loading the program latch with a second logic level signal complementary to the first logic level signal;

attempting to program a bit;

determining whether the bit has programmed; and

indicating a failed programming when the bit exhibits an erase threshold voltage.

3. A method of performing operations on a bitline in a memory device, comprising:

setting a bitline disable latch with a first logic signal indicating exclusion of the bitline or with a second complementary logic signal indicating that the bitline is available for operations; and

disabling the bitline for verification operation, wherein disabling the bitline for verification operation comprises pulling a verification node to ground.

4. A method of determining whether a programming operation on a bitline in a memory has failed, comprising:

loading a bitline disable latch with a first logic level signal;

loading a program latch with a second logic level signal complementary to the first logic level signal;

attempting to program a bit;

determining whether the bit has programmed; and

indicating a failed programming when the bit exhibits an erase threshold voltage.

5. The method of claim 4, and further comprising:

grounding a common node for the memory to indicate a failed programming operation.

6. The method of claim 5, wherein grounding the common node comprises:

turning on three transistors, the first transistor gate connected to a program verify signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to the bitline disable latch input signal.

7. A method of monitoring programming and verification on a bitline in a memory, comprising:

inhibiting operation of a program latch when a bitline is excluded from operation;

inhibiting operation of the program latch when a bitline is available for operations and the bitline fails a programming operation; and

indicating a failure of programming when the bitline fails the programming operation.

8. The method of claim 7, wherein indicating a failure comprises:

grounding a common node for the memory to indicate a failed programming operation.

9. The method of claim 8, wherein grounding the common node comprises:

turning on three transistors, the first transistor gate connected to a program verify signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to the bitline disable latch input signal.

10. A method of monitoring each of a plurality of bitlines in a memory for failed programming operation, comprising:

connecting a plurality of bitline disable circuits, each bitline disable circuit connected to a single bitline of the bitlines in the memory, to a common node;

precharging the common node;

discharging the common node when any of the plurality of bitline disable circuits indicate a failed programming operation.

11. A method of verifying programming on a bitline in a memory, comprising:

precharging a common node for the memory;

checking for a failed program operation on any of a plurality of programming latches in the memory;

discharging the common node when any of the plurality of program latches fails to program; and

asserting a fail signal in response to the discharge of the common node.

12. The method of claim 11, wherein discharging the common node comprises:

turning on three transistors, the first transistor gate connected to a program verify signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to the bitline disable latch input signal.

13. A method of programming a bit on a bitline, comprising:

loading a bitline disable latch with a first logic signal indicating a valid operational bitline;

loading a program latch with a complement to the first logic signal;

conditioning a bitline; and

initiating a program operation on the bitline.

14. The method of claim 13, and further comprising:

verifying programming on the bitline.

15. The method of claim 14, wherein verifying programming on the bitline comprises:

precharging a sense node;

precharging a bitline;

sensing the bit on the bitline;

maintaining the status of the program latch output when an erase threshold is sensed; and

switching the status of the program latch output when a program voltage is sensed.

16. The method of claim 15, and further comprising:

indicating a failed programming when maintaining is indicated.

17. The method of claim 16, wherein indicating a failed programming comprises:

discharging a node common to each of the circuits.

18. The method of claim 15, wherein switching status comprises:

pulling the output node of the program latch to a second logic level through a discharge path when switching is indicated.

19. The method of claim 18, and further comprising:

inhibiting program latch operation when switching is indicated.

20. A memory device, comprising:

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising;

a program latch to initiate programming of the memory; and

a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated.

21. The memory device of claim 20, wherein the circuit further comprises:

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

22. The memory device of claim 20, wherein the circuit further comprises:

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.

23. The memory device of claim 20, wherein the memory device is a NAND memory device.

24. The memory device of claim 20, wherein the memory device is a flash memory device.

25. The memory device, of claim 20, wherein the memory device is a non-volatile memory device.

26. A non-volatile memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections;

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory; and

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

27. The memory device of claim 26, wherein the non-volatile memory device further comprises a bitline disable circuit comprising:

a program latch to initiate programming of the memory;

a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated.

28. The memory device of claim 26, wherein the non-volatile memory device further comprises:

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.

29. An integrated circuit, comprising:

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing when a sensed bit on the bitline is programmed.

30. A bitline disable circuit, comprising:

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and ground.

31. A program verify circuit, comprising:

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal.

32. A read/verify sense circuit, comprising:

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.

33. A processing system, comprising:

a processor; and

a memory device coupled to the processor to store data provided by the processor and to provide data to the processor, the memory comprising;

an array of memory cells;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising;

a program latch to initiate programming of the memory;

a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated.

34. The system of claim 33, wherein the circuit further comprises:

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

35. The system of claim 33, wherein the circuit further comprises:

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.

36. The system of claim 33, wherein the circuit further comprises:

a bitline disable circuit comprising;

a bitline disable latch having an input and an output;

a program latch having an input and an output; and

a first transistor having a gate connected to the output of the bitline disable latch and source to drain connected between the output of the program latch and a ground potential;

a program verify circuit comprising;

second, third, and fourth transistors connected in series between a charged node and a ground potential, the second transistor gate connected to a verification enable signal, the third transistor gate connected to the program latch output signal, and the fourth transistor gate connected to the bitline disable latch input signal; and

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of the program latch on sensing when a sensed bit on the bitline is programmed.

37. The system of claim 33, wherein the memory device is a NAND memory device.

38. A flash memory device, comprising:

an array of floating gate memory cells;

control circuitry to read, write and erase the floating gate memory cells; and

address circuitry to latch address signals provided on address input connections; and

a circuit to exclude a bad bitline from memory operations and to detect a failed program sequence on a bitline for each of a plurality of bitlines in the memory, the circuit comprising;

a program latch to initiate programming of the memory;

a bitline disable latch programmable to inhibit operation of the program latch when a bad bitline is indicated.

39. The flash memory device of claim 38, wherein the non-volatile memory device further comprises:

a program verify circuit comprising;

first, second, and third transistors connected in series between a charged node and a ground potential, the first transistor gate connected to a verification enable signal, the second transistor gate connected to a program latch output signal, and the third transistor gate connected to a bitline disable latch signal, wherein the node is discharged to ground.

40. The flash memory device of claim 38, wherein the non-volatile memory device further comprises:

a read/verify sense circuit comprising;

a sense precharge transistor source to drain connected between a supply voltage and a sense node;

a bitline sense transistor source to drain connected between the sense node and a bitline; and

a transistor gate connected to the sense node, to inhibit operation of a program latch on sensing when a sensed bit on the bitline is programmed.