Method and architecture to calibrate read operations in synchronous flash memory
First Claim
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1. A method of calibrating a non-volatile memory comprising:
- storing a test pattern in the non-volatile memory;
reading the test pattern with a first read circuit;
reading the test pattern with a second read circuit;
determining if an offset of what is read as a programmed and/or erased non-volatile memory cell exists between the first and second read circuits; and
adjusting either the first or second read circuit if an offset is determined.
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Abstract
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection of the output buffer with the read sense amplifier and the verification sense amplifier. By measuring the distributions of voltage thresholds of erased cells versus voltage thresholds of programmed cells, differences in offsets between read state and write state of memory cells are determined. A specific margin is determined to ensure proper reads of the memory cells.
122 Citations
25 Claims
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1. A method of calibrating a non-volatile memory comprising:
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storing a test pattern in the non-volatile memory; reading the test pattern with a first read circuit; reading the test pattern with a second read circuit; determining if an offset of what is read as a programmed and/or erased non-volatile memory cell exists between the first and second read circuits; and adjusting either the first or second read circuit if an offset is determined. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of calibrating sense amplifiers and read paths comprising:
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reading a data state of a plurality of memory cells through a first read path with a first sense amplifier; reading the data state of the plurality of memory cells through a second read path with a second sense amplifier; comparing outputs of the first and second sense amplifiers to determine offsets between the first read path and first sense amplifier and the second read path and second sense amplifier; and adjusting input voltage levels and/or read timing of either the first or second sense amplifier to calibrate what is read as a programmed and/or erased memory cell the first read path and first sense amplifier and the second read path and second sense amplifier. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A method of calibrating read and write operations of a non-volatile memory comprising:
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reading a data state of a plurality of programmed or erased memory cells through a first read path with a first sense amplifier; reading the data state of the plurality of programmed or erased memory cells through a second read path with a second sense amplifier; comparing outputs of the first and second sense amplifiers to determine offsets between the first read path and first sense amplifier and the second read path and second sense amplifier; and adjusting input voltage levels and/or read timing of either the first or second sense amplifier to calibrate what is read as a programmed and/or erased memory cell the first read path and first sense amplifier and the second read path and second sense amplifier. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25)
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Specification