Digital signal receiver operating beyond the -3dB frequency

• US 7,274,756 B2
• Filed: 07/17/2002
• Issued: 09/25/2007
• Est. Priority Date: 07/18/2001
• Status: Expired due to Fees

• Current Assignee: Vrije Universiteit Brussel
• Original Assignee: Vrije Universiteit Brussel
• Inventors: Kuijk, Maarten
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): Flores; Leon
• Application Number:
  US10/483,207
• Publication Number:
  US 20040208265A1
• Time in Patent Office: 1,896 Days
• Field of Search: 327/335, 327/558, 375/340, 375/257, 375/214, 375/345, 375/316
• US Class Current: 375/340
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

A receiver for digital data connects to a preceding signal path and the digital data has a lower to upper data frequency range. The receiver includes a received signal input terminal connected to a higher frequency gain circuit that shows highest transfer amplitude at the upper data frequency within the lower to upper data frequency range where the signal has been attenuated in its higher frequency components in the preceding signal path and providing an amplified signal at an amplified signal output terminal. The receiver further includes a latching circuit with two threshold levels, the latching circuit is connected with an input terminal to the amplified signal output terminal and an output terminal providing a digital output signal.

Claims

1. A receiver for digital data for connection to a preceding signal path, said digital data having a lower to upper data frequency range, comprising:

a received signal input terminal connected to a higher frequency gain circuit that has highest transfer amplitude at said upper data frequency within said lower to upper data frequency range where the signal has been attenuated in its higher frequency components in said preceding signal path and providing an amplified signal at an amplified signal output terminal and wherein the higher frequency gain circuit together with said attenuation in said preceding signal path has a slope in the transfer amplitude of +20 dB/decade at said upper data frequency; and

a latching circuit with two threshold levels, said latching circuit being connected with an input terminal to said amplified signal output terminal and an output terminal providing a digital output signal.

2. The receiver for digital data as in claim 1, wherein said latching circuit comprises a latch and two comparators.

3. The receiver for digital data as in claim 1, wherein said latching circuit is a Schmitt trigger.

4. The receiver for digital data as in claim 1, said higher frequency gain circuit further having a transfer function with increasing amplitude for increasing frequency in said lower to upper data frequency range and that starts to decrease in amplitude from a frequency that is higher than said upper data frequency.

5. The receiver for digital data as in claim 1, wherein the received signal input terminal is arranged to receive a differential signal between two input nodes.

6. The receiver for digital data as in claim 1, wherein the received signal input terminal comprises one input node arranged to receive the signal.

7. The receiver for digital data as in claim 1, wherein the higher frequency gain circuit has a transfer function that in amplitude remains equal or decreases for increasing frequencies from said upper data frequency onwards.

8. The receiver for digital data as in claim 1, wherein the latching circuit has a positive threshold and a negative threshold.

9. The receiver for digital data as in claim 1, wherein the output of the latching circuit switches from HIGH to LOW when the signal at its input terminal increases above said positive threshold the output switches from LOW to HIGH when the signal at its input terminal decreases below said negative threshold and the swing of said signal at said input terminal is between 1.5 to 5 times larger than the difference between said positive and said negative threshold.

10. The receiver for digital data as in claim 1, further comprising an auto gain circuit that changes an amplification factor in said higher frequency gain circuit in a way that the signal swing at said input of said latching circuit remains substantially at a predefined target value.

11. The receiver for digital data as in claim 1, further comprising a negative feedback loop arranged to bring the average signal at said input terminal of said latching circuit to essentially halfway between said positive and said negative threshold.

12. The receiver for digital data as in claim 1, wherein the higher frequency gain circuit comprises a differentiator stage.

13. The receiver as in claim 12, wherein the higher frequency gain circuit further composes a gain stage.

14. The receiver for digital data as in claim 1, wherein a non-differential signal is received, the higher frequency gain circuit having a capacitor at its input.

15. The receiver for digital data as in claim 1, wherein a differential signal is received, the higher frequency gain circuit having a capacitor connected to each of its two said input nodes.

16. The receiver for digital data as in claim 1 wherein said slope is present in the frequency range between one eighth of said upper data frequency and said upper data frequency itself.

17. A method for receiving digital data from a preceding signal path, said digital data having a lower to upper data frequency range, where the signal has been attenuated in its higher frequency components in said preceding signal path, comprising the steps of:

providing a receiver such as in claim 1,

feeding said digital signal to the higher frequency gain circuit of said receiver and providing an amplified signal at an amplified signal output terminal; and

feeding said amplified signal to the latching circuit of said receiver and providing a digital output signal at the output terminal of the latching circuit.