Method and system for dynamically operating memory in a power-saving error correcting mode
First Claim
1. A method of storing data in a dynamic random access memory (“
- DRAM”
) device in either a normal operating mode when the DRAM device is active or a power-saving mode when the DRAM is inactive, the method comprising;
in the normal operating mode, refreshing memory cells in the DRAM device at a first rate, the memory cells being refreshed without being scrubbed in the normal operating mode; and
in the power-saving mode, scrubbing the memory cells in the DRAM device at a second rate that is substantially less than the first rate.
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Accused Products
Abstract
A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.
106 Citations
15 Claims
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1. A method of storing data in a dynamic random access memory (“
- DRAM”
) device in either a normal operating mode when the DRAM device is active or a power-saving mode when the DRAM is inactive, the method comprising;in the normal operating mode, refreshing memory cells in the DRAM device at a first rate, the memory cells being refreshed without being scrubbed in the normal operating mode; and in the power-saving mode, scrubbing the memory cells in the DRAM device at a second rate that is substantially less than the first rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- DRAM”
-
11. A dynamic random access memory (“
- DRAM”
) device, comprising;an array of memory cells arranged in rows and columns; an addressing circuit receiving and decoding an external address; a data path coupling data between a data bus and memory cells corresponding to the decoded memory address; a command decoder receiving and decoding external memory commands, the command decoder generating control signals for controlling the operation of the DRAM device, the command decoder further causing the DRAM device to operate in either a normal mode or a power-saving mode; a refresh controller operable to refresh the memory cells in the array at a first rate when the command decoder causes the DRAM device to operate in the normal mode; and a scrubbing controller operable to scrub the memory cells in the array at a second rate that is substantially less than the first rate when the command decoder causes the DRAM device to operate in the power-saving mode, the scrubbing controller further being operable to inhibit scrubbing of the memory cells when the command decoder causes the DRAM device to operate in the normal mode. - View Dependent Claims (12, 13, 14, 15)
- DRAM”
Specification