Methods of making microelectronic packages with conductive elastomeric posts

• US 7,276,400 B2
• Filed: 11/29/2005
• Issued: 10/02/2007
• Est. Priority Date: 12/12/1996
• Status: Expired due to Fees

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Fjelstad, Joseph
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US11/289,743
• Publication Number:
  US 20060084250A1
• Time in Patent Office: 672 Days
• Field of Search: 438/126
• US Class Current: 438/126
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/83856 Pre-cured adhesive, i.e. B-stage adhesive
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A method of making a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts that connect at least some of the contacts of the first microelectronic element to at least some of the contacts of the second microelectronic element, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.

Claims

1. A method of making a microelectronic assembly comprising:

providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface;

providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface;

forming a plurality of conductive elastomeric posts that connect at least some of the contacts of the first microelectronic element to at least some of the contacts of the second microelectronic element; and

injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.

2. The method as claimed in claim 1, wherein the conductive elastomeric posts comprise an elastomeric matrix and conductive particles.

3. The method as claimed in claim 1, wherein the second microelectronic element is a semiconductor chip.

4. The method as claimed in claim 1, further comprising juxtaposing the first surface of the first microelectronic element with the top surface of the second microelectronic element.

5. The method as claimed in claim 1, further comprising bonding the conductive elastomeric posts to at least some of the contacts of the first and second microelectronic elements.

6. The method as claimed in claim 1, further comprising planarizing the conductive elastomeric posts.

7. The method as claimed in claim 1, wherein one of the first and second microelectronic elements comprises a dielectric substrate wiring layer.

8. The method as claimed in claim 1, wherein the dielectric substrate wiring layer is flexible.

9. The method as claimed in claim 1, further comprising, after the injecting step, curing the compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element.

10. The method as claimed in claim 2, wherein the conductive particles are silver or gold.

11. The method as claimed in claim 2, wherein the elastomeric matrix is a silicone elastomer or a low modulus polymer blend.

12. The method as claimed in claim 2, wherein the conductive particles include a nonconductive portion and a conductive portion that surrounds the nonconductive portion.

13. The method as claimed in claim 1, wherein the first microelectronic element is a semiconductor chip.

14. The method as claimed in claim 4, wherein the juxtaposing step includes aligning at least one of the contacts of the first microelectronic element with at least one of the contacts of the second microelectronic element.

15. The method as claimed in claim 7, wherein the dielectric substrate wiring layer has conductive terminal accessible at one or more surfaces thereof.

16. A method of making a microelectronic assembly comprising:

providing a microelectronic element having a first surface and a plurality of contacts accessible at the first surface;

providing a dielectric substrate having a top surface and a plurality of contacts accessible at the top surface;

juxtaposing the first surface of the microelectronic element with the top surface of the dielectric substrate;

forming a plurality of conductive elastomeric posts that connect at least some of the contacts of the first microelectronic element to at least some of the contacts of the dielectric substrate; and

injecting a compliant material between the first surface of the first microelectronic element and the top surface of the dielectric substrate to form a compliant layer.

17. The method as claimed in claim 16, wherein the dielectric substrate comprises conductive traces overlying the top surface thereof.

18. The method as claimed in claim 16, wherein the dielectric substrate comprises metalized vias.

19. The method as claimed in claim 16, wherein the dielectric substrate comprises conductive traces extending between the top surface and a bottom surface thereof.

20. The method as claimed in claim 16, wherein the dielectric substrate is flexible.