Memory cell and method for forming the same

• US 7,276,418 B2
• Filed: 11/10/2005
• Issued: 10/02/2007
• Est. Priority Date: 06/21/2002
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Brown, Kris K.
• Primary Examiner(s): Dang; Phuc T.
• Application Number:
  US11/271,127
• Publication Number:
  US 20060063330A1
• Time in Patent Office: 691 Days
• Field of Search: 438/300, 438/303, 438/329, 438/341, 438/363, 438/366, 438/413, 257/300, 257/327, 257/330, 257/343, 257/407, 257/412
• US Class Current: 438/300
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor memory cell structure having 4F² dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Claims

1. A method for forming a plurality of memory cell structures on a surface of a substrate, comprising:

forming an active region in the substrate;

forming a plurality of posts on the surface of the substrate over the active region, the plurality of posts formed from a semiconductor material and spaced apart from one another by respective regions;

forming a plurality of contacts over and electrically coupled to the active region, each contact having at least a portion formed adjacent a respective one of the regions for a pair of posts;

forming a plurality of memory cell capacitors on a respective one of the plurality of posts; and

forming a plurality of gate structures adjacent a respective one of the plurality of posts to form a respective vertical transistor to electrically couple the respective memory cell capacitor to the active region.

3. The method of claim 1 wherein forming the plurality of contacts comprises forming each contact of the plurality of contacts adjacent a respective one of the regions for the pair of posts and equidistant from each of the posts of the pair.

4. The method of claim 1 wherein forming the plurality of contacts comprises forming each contact of the plurality of contacts having a first portion formed adjacent a respective one of the regions for a pair of posts and further having a second portion formed in the region between the pair of posts.

5. The method of claim 1 wherein forming the active region in the substrate comprises forming an active region extending laterally across the surface of the substrate and the plurality of posts formed over the active region comprises at least three posts.

6. The method of claim 1 wherein forming the plurality of posts comprises forming each post of the plurality of posts from a doped epitaxial silicon material.

7. The method of claim 1 wherein forming the plurality of posts comprises forming each post of the plurality of posts having first and second opposite lateral surfaces and forming the plurality of gate structures comprises forming each gate structure of the plurality of gate structures adjacent to the first and second opposite lateral surfaces of the respective post.

8. The method of claim 1 wherein forming the plurality of posts comprises forming each post of the plurality of posts having first and second adjacent lateral surfaces and forming the plurality of gate structures comprises forming each gate structure of the plurality of gate structures adjacent to the first and second adjacent lateral surfaces of the respective post.

9. The method of claim 1 wherein forming the plurality of memory cell capacitors comprises forming each memory cell capacitor of the plurality of memory cell capacitors having a container-shaped capacitor structure.

2. The method of 1 wherein forming the plurality of contacts comprises forming each contact of the plurality of contacts over a respective portion of the active region that extends laterally on the surface of the substrate from a respective region between a pair of posts.

10. A method for forming a plurality of memory cell structures on a surface of a substrate, comprising:

forming an active region in the substrate;

forming a semiconductor post on the active region;

forming first and second contacts on the active region and laterally disposed on opposite sides of the semiconductor post along the surface of the substrate;

forming a memory cell capacitor on the semiconductor post; and

forming a vertical access transistor having a gate adjacent the semiconductor post and to electrically couple the capacitor to the first and second contacts in response to being activated.

11. The method of claim 10 wherein forming the first and second contacts comprises forming the first and second contacts equidistant from the semiconductor post.

12. The method of claim 10 wherein forming the first and second contacts comprises forming the first and second contacts from a titanium material.

13. The method of claim 10 wherein forming the first and second contacts comprises forming the first and second contacts from a tungsten material.

14. The method of claim 10 wherein forming the first and second contacts comprises forming the first and second contacts from a metal material.

15. The method of claim 10 wherein forming the memory cell capacitor comprises:

forming a first capacitor plate layer from a first material;

forming a second capacitor plate layer from a second material; and

forming a dielectric layer disposed between the first and second capacitor plate layers.

16. The method of claim 15 wherein forming the dielectric layer comprises forming the dielectric layer from a layer of aluminum oxide.

17. The method of claim 15 wherein forming the dielectric layer comprises forming the dielectric layer from a layer of hafnium oxide.

18. The method of claim 15 wherein forming the first and second plates comprises forming the first and second plates from the same material.

19. The method of claim 15 wherein forming the first and second plates comprises forming the first and second plates from a titanium material.

20. The method of claim 15 wherein forming the first and second plates comprises forming the first and second plates from a tantalum material.

21. The method of claim 15 wherein forming the first and second plates comprises forming the first and second plates from a platinum material.

22. The method of claim 10 wherein forming the vertical access transistor comprises forming a gate structure from a titanium material.

23. The method of claim 10 wherein forming the vertical access transistor comprises forming a gate structure from a molybdenum material.

24. The method of claim 10 wherein forming the vertical access transistor comprises forming a gate structure from a nickel material.

25. The method of claim 10 wherein forming the vertical access transistor comprises forming a gate structure from a silicon material.