Method of manufacturing a passive integrated matching network for power amplifiers

• US 7,276,420 B2
• Filed: 07/11/2005
• Issued: 10/02/2007
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Li, Qiang, Liu, Lianjun, Miller, Melvy F., Pacheco, Sergio P.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/179,685
• Publication Number:
  US 20070007622A1
• Time in Patent Office: 813 Days
• Field of Search: 438/171, 438/190, 438/210, 438/329, 438/393
• US Class Current: 438/329
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching
• CPC Class Codes: H03H 7/38 : Impedance-matching networks

Abstract

An impedance matching network is integrated on a first die and coupled to a second die, with the first and second dies mounted on a conductive back plate. The impedance matching network comprises a first inductor bridging between the first and second dies, a second inductor coupled to the first inductor and disposed on the first die, and a metal-insulator-metal (MIM) capacitor disposed on the first die. The MIM capacitor has a first metal layer coupled to the second inductor, and a second metal layer grounded to the conductive back plate. A method for manufacturing the integrated impedance matching network comprises the steps of forming an inductor on a die, forming a capacitor on the die, coupling the capacitor to the inductor, coupling the die bottom surface and the capacitor to a conductive plate, and coupling the inductor to another inductor that bridges between the die and another die.

Claims

1. A method of manufacturing an integrated impedance matching network, the method comprising the steps of:

forming a first inductor on a first die having top and bottom surfaces;

forming a capacitor first metal layer on the first die top surface;

forming an insulator layer on the capacitor first metal layer;

forming a capacitor second metal layer on the insulator layer;

coupling the capacitor second metal layer to the first inductor;

mounting the first die bottom surface to a conductive plate;

coupling the capacitor first metal layer to the conductive plate; and

coupling the first inductor to a second inductor that bridges between the first die and a second die that is mounted on the conductive plate.

2. The method according to claim 1, wherein the first die comprises an insulating or semi-insulating substrate.

3. The method according to claim 2, wherein the first die comprises GaAs.

4. The method according to claim 1, wherein the first die is between about 75 and about 200 μ

m in thickness.

5. The method according to claim 1, wherein the second inductor comprises a plurality of bond wires, and the first inductor comprises a plurality of metal strips.

6. The method according to claim 5, wherein each of the metal strips is more than 8 μ

m in thickness, and more than 40 μ

m in width.

7. The method according to claim 5, wherein each of the bond wires is between about 10 mils and about 30 mils in height.

8. The method according to claim 1, wherein the second die is an LDMOS die.

9. The method according to claim 1, wherein the second die is a III-V compound semiconductor die.

10. The method according to claim 1, wherein the second die comprises a power amplification circuit.

11. The method according to claim 1, wherein the step of coupling the capacitor first metal layer to the conductive plate comprises the steps of:

forming a via hole through the first die before mounting the first die bottom surface; and

filling the via hole with an interconnect metal.

12. The method according to claim 1, wherein the first inductor, and the capacitor first and second metal layers are formed from the same materials.

13. The method according to claim 1, wherein the step of coupling the capacitor second metal layer to the first inductor includes forming a third metal layer that connects the capacitor second metal layer to the first inductor.

14. The method according to claim 13, wherein the first inductor, the capacitor first and second metal layers, and the third metal layer, are all formed from the same materials.

15. The method according to claim 1, wherein the integrated impedance matching network is part of a power amplifier for a base station that amplifies and transmits remote signals.

16. The method according to claim 1, wherein the step of forming the first inductor is performed while performing one or more of the steps of forming the capacitor first and second metal layers and the step of coupling the capacitor second metal layer to the first inductor.

17. A method of manufacturing an integrated impedance matching network, the method comprising the steps of:

forming a first inductor on a first die having top and bottom surfaces;

forming a first capacitor layer from a first metal on the first die top surface while forming the first inductor using the first metal;

forming an insulator layer on the capacitor first metal layer;

forming a second capacitor layer from a second metal on the insulator layer while continuing to form the first inductor using the second metal;

coupling the capacitor second metal layer to the first inductor;

mounting the first die bottom surface to a conductive plate;

coupling the capacitor first metal layer to the conductive plate; and

coupling the first inductor to a second inductor that bridges between the first die and a second die that is mounted on the conductive plate.

18. The method according to claim 17, wherein the step of coupling the capacitor second metal layer to the first inductor includes forming a layer from a third metal that connects the capacitor second metal layer to the first inductor, and that further forms the first inductor.

19. The method according to claim 17, wherein the step of coupling the capacitor first metal layer to the conductive plate comprises the steps of:

forming a via hole through the first die before mounting the first die bottom surface; and

filling the via hole with an interconnect metal.

20. The method according to claim 17, wherein the second inductor comprises a plurality of bond wires, and the first inductor comprises a plurality of metal strips.