Post passivation interconnection schemes on top of the IC chips

• US 7,276,422 B2
• Filed: 11/14/2005
• Issued: 10/02/2007
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/273,085
• Publication Number:
  US 20060060973A1
• Time in Patent Office: 687 Days
• Field of Search: 438/381, 438/393, 438/239, 438/240, 438/250, 438/622
• US Class Current: 438/381
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A method for fabricating a circuit component comprising:

providing a silicon substrate, a metallization structure over said silicon substrate, and a passivation layer over said metallization structure, wherein said metallization structure is formed by a process comprising electroplating; and

forming a passive device over said passivation layer, wherein said forming said passive device comprises;

depositing a first metal layer over said passivation layer,

after said depositing said first metal layer, forming a patterned photoresist layer,

after said forming said patterned photoresist layer, electroplating a second metal layer,

after said electroplating said second metal layer, removing said patterned photoresist layer, and

after said removing said patterned photoresist layer, etching said first metal layer.

2. The method of claim 1, wherein said metallization structure is formed by said process further comprising CMP.

3. The method of claim 1, wherein said passive device comprises an inductor.

4. The method of claim 1, wherein said passive device comprises a layer of gold.

5. The method of claim 1 further comprising providing a transistor in said silicon substrate.

6. The method of claim 1, wherein said forming said patterned photoresist layer comprising coating.

7. The method of claim 1, wherein said passivation layer is formed by a process comprising:

depositing an oxide layer, and

after said depositing said oxide layer, depositing a nitride layer.

8. The method of claim 1, wherein said depositing said first metal layer comprises sputtering.

9. The method of claim 1, wherein said passivation layer comprises a topmost nitride layer of said circuit component.

10. A method for fabricating a circuit component comprising:

providing a silicon substrate, a metallization structure over said silicon substrate, and a passivation layer over said metallization structure, wherein said silicon substrate comprises multiple semiconductor devices, and wherein said metallization structure is formed by a process comprising electroplating; and

forming an inductor over said passivation layer, wherein said forming said inductor comprises;

depositing a first metal layer over said passivation layer,

after said depositing said first metal layer, forming a patterned photoresist layer,

after said forming said patterned photoresist layer, electroplating a second metal layer,

after said electroplating said second metal layer, removing said patterned photoresist layer, and

after said removing said patterned photoresist layer, etching said first metal layer.

11. The method of claim 10, wherein said metallization structure is formed by said process further comprising CMP.

12. The method of claim 10 further comprising providing a transistor in said silicon substrate.

13. The method of claim 10, wherein said inductor comprises a layer of gold.

14. The method of claim 10, wherein said forming said patterned photoresist layer comprises coating.

15. The method of claim 10, wherein said passivation layer is formed by a process comprising:

depositing an oxide layer, and

after said depositing said oxide layer, depositing a nitride layer.

16. The method of claim 10, wherein said depositing said first metal layer comprises sputtering.

17. The method of claim 10, wherein said passivation layer comprises a topmost nitride layer of said circuit component.