Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors

• US 7,276,433 B2
• Filed: 12/03/2004
• Issued: 10/02/2007
• Est. Priority Date: 12/03/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US11/003,275
• Publication Number:
  US 20060121677A1
• Time in Patent Office: 1,033 Days
• Field of Search: 438/595, 438/596, 438/238
• US Class Current: 438/595
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

Claims

1. A method of forming memory circuitry comprising:

providing a silicon-comprising substrate comprising a memory array area and a peripheral circuitry area, the memory array area comprising a first pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate in at least a first cross-section of the substrate, the peripheral circuitry area comprising a second pair of spaced adjacent electrically conductive structures received over the silicon-comprising substrate at least in a second cross-section of the substrate, the conductive structures of the second pair being spaced further from one another in the second cross-section than are those of the first pair in the first cross-section;

depositing a masking material between the conductive structures of each of the first and second pairs;

removing the masking material effective to expose silicon between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section;

after the removing effective to expose silicon, depositing metal over the substrate and annealing the substrate effective to react the metal with silicon of the substrate to form an electrically conductive metal silicide between the conductive structures of the second pair in the second cross-section but not between the conductive structures of the first pair in the first cross-section; and

after the annealing, removing at least some of the masking material from between the conductive structures of the first pair in the first cross-section.

2. The method of claim 1 wherein the conductive structures of the first and second pairs are gates.

3. The method of claim 1 wherein the masking material is electrically insulative.

4. The method of claim 3 wherein the masking material comprises silicon nitride.

5. The method of claim 3 wherein the masking material comprises silicon dioxide.

6. The method of claim 1 wherein the masking material comprises amorphous carbon.

7. The method of claim 1 wherein the masking material comprises transparent carbon.

8. The method of claim 1 wherein the masking material is electrically conductive.

9. The method claim 8 wherein the masking material comprises a metal nitride.

10. The method of claim 9 wherein the masking material comprises tungsten nitride.

11. The method of claim 9 wherein the masking material comprises titanium nitride.

12. The method of claim 1 wherein the masking material is semiconductive.

13. The method of claim 1 wherein the removing comprises chemical etching.

14. The method of claim 1 wherein said depositing metal and annealing the substrate occur simultaneously over at least some period of time.

15. The method of claim 1 wherein said depositing metal and annealing the substrate occur over at least same non-simultaneous periods of time.

16. The method of claim 1 wherein said removing after the annealing is of all the masking material in the first cross-section.

17. The method of claim 1 wherein said removing after the annealing is of all said masking material from the substrate.

18. The method of claim 1 comprising forming an anisotropically etched electrically insulative sidewall spacer over a sidewall of at least one of the conductive structures in at least one of the first and second cross-sections prior to depositing the masking material.

19. The method of claim 1 wherein the depositing of the masking material through said removing of the masking material effective to expose silicon occurs without any photolithographic patterning within the first and second cross-sections.

20. The method of claim 1 wherein the depositing of the masking material through said removing of the masking material effective to expose silicon occurs without any photolithographic patterning anywhere on the substrate.