System and method for linearizing a CMOS differential pair

• US 7,276,970 B2
• Filed: 05/18/2005
• Issued: 10/02/2007
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Khorramabadi, Haideh
• Primary Examiner(s): NGUYEN, KHANH V
• Application Number:
  US11/131,281
• Publication Number:
  US 20050258901A1
• Time in Patent Office: 867 Days
• Field of Search: 330252-254, 327/359, 327/563
• US Class Current: 330/253
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 2201/0266 the means comprising a transistor
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2203/45318 : the AAC comprising a cross coupling circuit, e.g. two extra transistors cross coupled
• CPC Class Codes: H03F 2203/45704 : the LC comprising one or more parallel resonance circuits
• CPC Class Codes: H03F 3/191 : Tuned amplifiers H03F3/193, H03F3/195 take precedence
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages
• CPC Class Codes: H03F 3/45475 : using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 1/0029 : using FETs
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 1/023 : by using voltage variable capacitance diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their V_ds dynamically modified in conjunction with current steering of the differential pairs sources.

Claims

1. A system for generating a substantially linear differential pair amplifier output comprising:

means for generating at least a first error correction current for a first output drain current of a main differential pair amplifier having a first common constant current source;

means for generating at least a second error correction current for a second output drain current of said main differential pair amplifier;

means for combining said first error correction current with said first output drain current; and

means for combining said second error correction current with said second output drain current;

wherein said first and second error correction currents are out of phase with corresponding first and second output drain currents of said main differential pair amplifier; and

wherein said first and second error correction currents are generated using a second common constant current source that is a fraction of the first common constant current source.

2. The system of claim 1, wherein amplitudes of said first and second error correction currents are a fraction of corresponding amplitudes of said first and second output drain currents.

3. The system of claim 1, wherein said first and second error correction currents improve linearity of said first and second output drain currents.

4. The system of claim 1, wherein said main differential pair amplifier is a common source Complementary Metal Oxide Semiconductor (CMOS) differential pair amplifier.

5. The system of claim 1, wherein said first and second error correction currents are generated by at least one auxiliary differential pair amplifier.

6. The system of claim 5, wherein said auxiliary differential pair amplifier is a common source Complementary Metal Oxide Semiconductor (CMOS) amplifier.

7. The system of claim 1, wherein said first error correction current is approximately 180 degrees out of phase with said first output drain current.

8. The system of claim 1, wherein said second error correction current is 180 degrees out of phase with said second output drain current.

9. A method to optimize linearity of a differential pair amplifier output comprising:

generating first and second output drain currents from a main differential pair amplifier having a first common constant current source;

generating a first and second drain current from an auxiliary differential pair amplifier having a second common constant current source;

combining said first drain current and said first output drain current and combining said second drain current and said second output drain current; and

generating a substantially linear output from said first and second output drain currents;

wherein said first output drain current is approximately 180 degrees out of phase with said first drain current and said second output drain current is approximately 180 degrees out of phase with said second drain current;

wherein said second common constant current source is a fraction of said first common constant current source.

10. The system of claim 9, wherein amplitudes of said first and second drain currents are a fraction of corresponding amplitudes of said first and second output drain currents.

11. The system of claim 9, wherein said first and second drain currents improve linearity of said first and second output drain currents.

12. The method of claim 9, wherein said main differential pair amplifier and said auxiliary differential pair amplifier are common source Complementary Metal Oxide Semiconductor (CMOS) differential amplifiers.

13. An amplification system to generate a substantially linear output comprising:

a main common source differential pair amplifier having a first constant current common source and first and second output drains;

a first auxiliary common source differential pair amplifier having a second constant current common source;

a second auxiliary common source differential pair amplifier having a third constant current common source;

wherein a first and second output drains of said main common source differential pair amplifier are coupled to corresponding first and second drains of said auxiliary differential pair amplifiers that are approximately 180 degrees out of phase with said first and second output drains.

14. The amplification system of claim 13, wherein amplitude of each of said first and second drain currents of said auxiliary differential pair amplifiers is a fraction of amplitude of said first and second output drain currents of said main differential pair amplifier.

15. The amplification system of claim 13, wherein said first and second drain currents of said auxiliary differential pair amplifiers improve linearity of said first and second output drain currents.

16. The amplification system of claim 13, wherein said main differential pair amplifier and said auxiliary differential pair amplifiers are Complementary Metal Oxide Semiconductor (CMOS) common source differential amplifiers.

17. The amplification system of claim 13, wherein said second and third constant current sources are a fraction of said first constant current source.