Triple cascode power amplifier of inner parallel configuration with dynamic gate bias technique
First Claim
1. A power amplifier, comprising:
- a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage;
a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal from the second transistor to the output end after re-amplification; and
a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain node of the third transistor, and a ground in series, and provides the dynamic gate bias to a gate of the third transistor by distributing an output signal at the drain of the third transistor through the first and second capacitors.
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Abstract
Provided is a power amplifier which fits to a deep-submicron technology in radio frequency wireless communication. The power amplifier includes a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain of the third transistor, and a ground in series, and provides the dynamic bias to a gate of the third transistor.
69 Citations
9 Claims
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1. A power amplifier, comprising:
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a cascode including a first transistor which receives and amplifies an input signal, and a second transistor which is connected to the first transistor in series and operated by a DC bias voltage; a third transistor which is connected between the cascode and an output end, operated by a dynamic gate bias and outputting a signal from the second transistor to the output end after re-amplification; and a voltage divider which includes first and second capacitors that are connected between the output end, i.e. a drain node of the third transistor, and a ground in series, and provides the dynamic gate bias to a gate of the third transistor by distributing an output signal at the drain of the third transistor through the first and second capacitors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification
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- Resources
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Current AssigneeElectronics and Telecommunications Research Institute
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Original AssigneeElectronics and Telecommunications Research Institute
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InventorsYu, Hyun-Kyu, Kim, Cheon-Soo, Park, Mun-Yang, Oh, Hyoung-Seok
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Primary Examiner(s)Choe; Henry
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Application NumberUS11/267,243Publication NumberTime in Patent Office697 DaysField of Search330/98, 330/150, 330/302, 330/310, 330/311US Class Current330/311CPC Class CodesH03F 1/223 with MOSFET'sH03F 1/301 in MOSFET amplifiers H03F1/...H03F 2200/27 A biasing circuit node bein...H03F 2203/7206 the gated amplifier being s...H03F 3/191 Tuned amplifiers H03F3/193,...H03F 3/72 Gated amplifiers, i.e. ampl...
