Arithmetic method and apparatus and crypto processing apparatus for performing multiple types of cryptography

• US 7,277,540 B1
• Filed: 01/19/2000
• Issued: 10/02/2007
• Est. Priority Date: 01/20/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawamura, Shinichi, Shiba, Masue
• Primary Examiner(s): Zand; Kambiz
• Assistant Examiner(s): Simitoski; Michael J.
• Application Number:
  US09/487,483
• Time in Patent Office: 2,813 Days
• Field of Search: 708/491, 708/492, 708/654, 708/655, 708/513, 708/603, 708/620, 708/523, 708/7, 708/135, 708/501, 708/503, 713/174, 380/265, 380/37, 380/30, 380/28, 714/808, 709/492
• US Class Current: 380/28
• CPC Class Codes: G06F 7/72 using residue arithmetic
• CPC Class Codes: G06F 7/722 Modular multiplication G06F7/724, G06F7/727, G06F7/728 take precedence
• CPC Class Codes: G06F 7/724 Finite field arithmetic for error detection or correction in general H03M13/00, in computers G06F11/10

Abstract

An arithmetic apparatus for performing a long product-sum operation includes an integer unit arithmetic circuit, a finite field GF(2^m) based unit arithmetic circuit logically adjacent to the integer unit arithmetic circuit, a selector for selecting the integer unit arithmetic circuit or the finite field GF(2^m) based unit arithmetic circuit, and an adder circuit which has a buffer for storing interim result data, adds the interim result data to the result data obtained by one of the integer unit arithmetic circuit and the finite field GF(2^m) based unit arithmetic circuit which is selected by the selector, propagates a carry in an integer unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.

Claims

1. An arithmetic apparatus incorporated in a LSI for performing a long integer product-sum arithmetic operation, the arithmetic apparatus comprising:

an arithmetic unit comprising;

an integer based multiplier circuit;

a finite field GF(2^m)-based multiplier circuit logically adjacent to but separated from said integer based multiplier circuit;

an adder circuit shared by the separated integer based multiplier circuit and the finite field GF(2^m)-based circuit and configured to operate on data from either the integer based multiplier circuit or the finite field GF(2^m)-based circuit; and

a selector configured to select one of said integer multiplier circuit and said finite field GF(2^m)-based multiplier circuit, and

a controller controlling said selector to make said selection.

2. An apparatus according to claim 1, wherein:

the adder circuit has a buffer for storing interim result data, adds the interim result data to result data from one of said integer based multiplier circuit and said finite field GF(2^m)-based multiplier circuit which is selected by said selector, propagates a carry in an integer based unit arithmetic operation, and propagates no carry in a finite field GF(2^m) based unit arithmetic operation.

3. An apparatus according to claim 2, wherein the arithmetic unit further comprises:

a carry holder for storing a carry obtained in a previous operation cycle, and an output-stage adder circuit configured to add the carry in said carry holder to an output from said adder circuit, output an upper bit of an addition result as an updated carry to said carry holder, and output a lower bit of the addition result as operation result data.

4. A crypto processing apparatus for selectively encrypting or decrypting based on an integer based operation by said arithmetic apparatus defined in claim 1, and encrypting or decrypting based on a finite field GF(2^m) based unit arithmetic operation by said arithmetic apparatus.