Network device interface for digitally interfacing data channels to a controller via a network

• US 7,277,970 B2
• Filed: 12/03/2003
• Issued: 10/02/2007
• Est. Priority Date: 12/08/2000
• Status: Expired due to Term

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Konz, Daniel W., Ellerbrock, Philip J., Grant, Robert L., Winkelmann, Joseph P.
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US10/726,918
• Publication Number:
  US 20040111536A1
• Time in Patent Office: 1,399 Days
• Field of Search: 710/21, 710/25, 710/53, 710/62, 710/69, 710/72, 700/286, 700/292, 700/22, 709/201, 709/238
• US Class Current: 710/62
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/4135 using bit-wise arbitration
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 2012/4028 the transportation system being an aircraft
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

The present invention provides a network device interface and method for digitally connecting a plurality of data channels, such as sensors, actuators, and subsystems, to a controller using a network bus. The network device interface interprets commands and data received from the controller and polls the data channels in accordance with these commands. Specifically, the network device interface receives digital commands and data from the controller, and based on these commands and data, communicates with the data channels to either retrieve data in the case of a sensor or send data to activate an actuator. Data retrieved from the sensor is converted into digital signals and transmitted to the controller. In some embodiments, network device interfaces associated with different data channels coordinate communications with the other interfaces based on either a transition in a command message sent by the bus controller or a synchronous clock signal.

Claims

1. A method for controlling a plurality of data channels connected via a common data bus to a bus controller, the method comprising:

transmitting a message including a command from the bus controller to the plurality of data channels, wherein the message comprises a plurality of bits having a value defined by a transition between first and second states, wherein the message is issued in a serial manner; and

performing a function defined by the command at each of the plurality of the data channels, wherein the data channels are connected to the common data bus in parallel to perform predefined functions as parallel processes to thereby support high speed communication over said common data bus, wherein performing the function comprises commencing performance of the function at each data channel at the same predetermined time using a predetermined transition in the message as a trigger, such that the plurality of data channels can perform the function simultaneously in a time-deterministic manner.

2. A method according to claim 1 wherein transmitting the message comprises transmitting the message either asynchronously or at a predetermined bit rate independent of an accompanying synchronous clock signals.

3. A method according to claim 1 wherein commencing performance of the function comprises commencing performance of the function at each data channel coincident with a predetermined transition defined in the message.

4. A method according to claim 1 wherein transmitting the message comprises transmitting a message including a command from the bus controller to the plurality of data channels, wherein the message comprises a plurality of bits, wherein the message comprises a sync portion, a message body and a parity bit, and wherein commencing performance of the function comprises commencing performance of the function at each data channel coincident with the transition that defines the value of the parity bit.

5. A method according to claim 1 wherein transmitting the message comprises transmitting a message comprising a start bit, a command field, an address field having an unused last bit set to 0, and a stop bit set to 1, and wherein commencing performance of the function comprises commencing performance of the function at each data channel coincident with the transition from the address bit to the stop bit.

6. A system for controlling a plurality of data channels connected via a common data bus to a bus controller, the system comprising:

a plurality of network device interfaces adapted to interconnect respective data channels with the bus controller via a common digital bus, wherein the data channels are connected to the common data bus in parallel to perform predefined functions as parallel processes to thereby support high speed communication over said common data bus, wherein each network device comprises;

a receiver for receiving a message from the bus controller via the common digital bus, wherein the message is comprised of a plurality of bits having a value defined by a transition between first and second states and is issued in a serial manner; and

a device interface for providing commands to the associated data channel in response to a message received by said receiver and for receiving data from the associated data channel,

wherein when said device interface of each network device interface receives a selected command from the bus controller, each device interface provides the command to the associated data channel at the same predetermined time using a predetermined transition in the message as a trigger, such that the plurality of data channels can perform the function simultaneously in a time-deterministic manner.

7. A system according to claim 6 wherein each network device interface further comprises a transmitter for transmitting messages including the data received by said network device interface from a data channel to the bus controller via the common digital bus.

8. A system according to claim 6 wherein said receiver of each network device interface is capable of receiving the message either asynchronously or at a bit rate from a predetermined set of bit rates independent of any accompanying synchronous clock signals.

9. A system according to claim 8 wherein said transmitter of each network device interface transmits messages at the same bit rate that said receiver received the message.

10. A system according to claim 6 wherein said receiver of each network device interface provides the commands to the associated data channel coincident with a predetermined transition in the message.

11. A system according to claim 6 wherein said receiver of each network device interface receives messages having a plurality of bits, wherein the messages comprises a sync portion, a message body and a parity bit, and wherein said device interface of each network device interface provides the commands to the associated data channel coincident with the transition that defines the value of the parity bit of the message.

12. A system according to claim 6 wherein said receiver of each network device interface receives messages comprised of a start bit, a command field, an address field having an address bit set to 0, and a stop bit set 1, and wherein said device interface of each network device interface provides the commands to the associated data channel coincident with the transition from the address bit to the stop bit.

13. A method for controlling a plurality of data channels connected via a common data bus to a bus controller, the method comprising:

transmitting a message including a command from the bus controller to the plurality of data channels, wherein the message comprises a plurality of bits having a value defined by a transition between first and second states, wherein the message is issued in a serial manner, and wherein the data channels are connected to the common data bus in parallel to perform predefined functions as parallel processes to thereby support high speed communication over said common data bus;

transmitting a synchronous clock signal comprised of a plurality of clock pulses from the bus controller to the plurality of data channels simultaneous with the message; and

performing a function defined by the command at each of the plurality of data channels, wherein performing the function comprises commencing performance of the function at each data channel at the same predetermined time as defined by a respective clock pulse which, in turn, is defined based upon a predetermined relationship to a respective bit of the message, where the respective bit is used as a trigger such that the plurality of data channels can perform the function simultaneously in a time-deterministic manner.

14. A method according to claim 13 wherein commencing performance of the function comprises commencing performance of the function at each data channel in synchronization with an edge of a first clock pulse following the respective bit of the message.

15. A method according to claim 13 wherein transmitting the message comprises transmitting a message comprising a plurality of bits having a value defined by a transition between a first state and a second state, wherein the bits of the message define a sync portion, a message body and a parity bit, and wherein commencing performance of the function comprises commencing performance of the function at each data channel at the same predetermined time as defined by a respective edge of a clock pulse which is, in turn, defined based upon a predetermined relationship to the transition that defines the value of the parity bit of the message.

16. A system for controlling a plurality of data channels connected via a common data bus to a bus controller, the system comprising:

a plurality of network device interfaces adapted to interconnect respective data channels with a bus controller via a common digital bus, wherein the data channels are connected to the common data bus in parallel to perform predefined functions as parallel processes to thereby support high speed communication over said common data bus, each network device interface comprising;

a receiver for receiving a message and a synchronous clock signal from the bus controller via the common digital bus, wherein the message is comprised of a plurality of bits having a value defined by a transition between first and second states and is issued in a serial manner, and wherein the synchronous clock signal is comprised of a plurality of clock pulses; and

a device interface for providing commands to the associated data channel in response to a message received by said receiver and for receiving data from the associated data channel,

wherein when said device interface of each network device interface receives a selected command from the bus controller, each device interface provides the command to the associated data channel at the same predetermined time as defined by a respective clock pulse which is defined using a predetermined relationship to a respective bit of the message as a trigger, thereby enabling the data channels associated with the plurality of interfaces to function synchronously.

17. A system according to claim 16 wherein each network device interface further comprises a transmitter for transmitting messages including the data received by said network device interface from an associated data channel to the bus controller via the common digital bus.

18. A system according to claim 17 wherein said transmitter of each network device interface transmits messages in either asynchronously on in synchronization with the synchronous clock signal.

19. A system according to claim 16 wherein said device interface of each network device interface provides the commands to the associated data channel in synchronization with an edge of the first clock pulse following the respective bit of the message.

20. A system according to claim 16 wherein said receiver receives a message comprising a plurality of bits having a value defined by a transition between a first state and a second state, wherein the bits of the message define a sync portion, a message body and a parity bit, and wherein said device interface of each network device interface provides the commands to the associated data channel at the same predetermined time as defined by a respective edge of a clock pulse which is, in turn, defined based upon a predetermined relationship to the transition that defines the value of the parity bit of the message.

21. A system according to claim 16 wherein said receiver receives a message comprising a plurality of bits which are Universal Asynchronous Receiver Transmitter non-return-to-zero encodes, wherein said device interface of each network device interface provides the commands to the associated data channel at the same predetermined time as defined by a respective clock pulse which is defined based upon a predetermined relationship to the transition between the address and stop bits of the message.