Method and apparatus for responding to access errors in a data processing system
First Claim
1. A data processing system having a processor coupled to a bus, the data processing system comprising:
- access error detection circuitry, coupled to the bus, the access error detection circuitry detecting an access error which occurs on a data or instruction access on the bus; and
access error response circuitry, coupled to the bus, the access error response circuitry initiating replacement of an existing value on the bus with a predetermined value rather than the existing value is provided to the processor, and the access error response circuitry continuing to replace the existing value on the bus with the predetermined value when the access error has been detected and a first indicator has been asserted, wherein the predetermined value has a selectable bit-ordering, wherein the selectable bit-ordering is one of big endian and little endian, wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second one of the plurality of modes, and wherein the first value and the second value are not a same value.
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Accused Products
Abstract
In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.
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Citations
23 Claims
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1. A data processing system having a processor coupled to a bus, the data processing system comprising:
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access error detection circuitry, coupled to the bus, the access error detection circuitry detecting an access error which occurs on a data or instruction access on the bus; and access error response circuitry, coupled to the bus, the access error response circuitry initiating replacement of an existing value on the bus with a predetermined value rather than the existing value is provided to the processor, and the access error response circuitry continuing to replace the existing value on the bus with the predetermined value when the access error has been detected and a first indicator has been asserted, wherein the predetermined value has a selectable bit-ordering, wherein the selectable bit-ordering is one of big endian and little endian, wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second one of the plurality of modes, and wherein the first value and the second value are not a same value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A data processing system, comprising:
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a processor; an instruction bus coupled to transfer instructions to and from the processor; a data bus coupled to transfer data to and from the processor; access error detection circuitry, coupled to the instruction bus and to the data bus, the access error detection circuitry detecting an access error in the data processing system; and access error response circuitry, coupled to the instruction bus and to the data bus, the access error response circuitry initiating replacement of an existing instruction value on the instruction bus with a predetermined instruction value when the access error has been detected wherein the predetermined instruction value rather than the existing instruction value is provided to the processor, said access error response circuitry continuing to replace the existing instruction value on the instruction bus with the predetermined instruction value when the access error response circuitry stops replacing the existing instruction value on the instruction bus with the predetermined instruction value when a second indicator is received from the processor indicative of the processor executing a software interrupt or an exception, and wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second one of the plurality of modes, and wherein the first value and the second value are not a same value. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method for responding to an access error in a data processing system, comprising:
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detecting an access error in the data processing system; determining which one of a plurality of modes is a current mode of the data processing system; replacing an existing bus value with a predetermined value when the access error is detected, wherein the predetermined value has a first value if the current mode of the data processing system is a first one of the plurality of modes, and wherein the predetermined value has a second value if the current mode of the data processing system is a second one of the plurality of modes, and wherein the first value and the second value are not a same value. - View Dependent Claims (21, 22, 23)
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Specification