Data transmission apparatus for high-speed transmission of digital data and method for automatic skew calibration

• US 7,278,069 B2
• Filed: 04/30/2003
• Issued: 10/02/2007
• Est. Priority Date: 10/31/2000
• Status: Expired due to Term
• 

• Current Assignee: Computer Circuit Operations LLC
• Original Assignee: Top Box Assets LLC (Intellectual Ventures LLC)
• Inventors: Deas, Alexander Roger, Abrosimov, Igor Anatolievich, Atyunin, Vasily Grigorievich, Klotchkov, Ilya Vasilievich
• Primary Examiner(s): Lamarre; Guy J.
• Application Number:
  US10/425,630
• Publication Number:
  US 20030198309A1
• Time in Patent Office: 1,616 Days
• Field of Search: 714/700, 714/744, 713/503, 307/409, 327/141, 327/292
• US Class Current: 714/700
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H04L 25/026 Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers duplexing arrangements H04L5/14

Abstract

A data transmission apparatus and method employing the phase noise characteristics within the receiving registers to measure and control the characteristics of the channel as a function of the data pattern and to compensate for production tolerances within the channel by altering the timing characteristics of the signal at either the transmitter or receiver as a function of the data. Time offsets between different signals that form the communication channel are measured for different frequencies and/or for different data patterns transmitted through the channel and stored to compensate for an inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

Claims

1. A data transmission apparatus for high-speed transmission of digital data comprising

a communicational channel between at least one transmitter having one or more registers for transmitting a signal along the communication channel, and at least one receiver having one or more registers for receiving the signal;

a main clock for generating a main clock signal for said transmitter'"'"'s register(s); and

a reference clock for generating reference signals for calibrating said receiver'"'"'s register(s);

said reference clock being associated with said main clock;

a means for measuring time offsets between different signals that form the communication channel, at different frequencies, and/or for different data patterns transmitted through the channel;

a storage means for recording and storing the measured time offsets; and

a timing correction means for applying the measured time offsets to compensate for inter-signal skew by performing relative alignment of the measured offsets to the main clock edge.

2. The apparatus according to claim 1, wherein each of said timing correction means is pre-calibrated by varying a calibration frequency.

3. The apparatus according to claim 1, wherein said timing correction means is chosen from variable delay, programmable delay, analogue vernier, digital vernier.

4. The apparatus according to claim 1, wherein the timing correction means generates and applies a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means.

5. The apparatus according to claim 1, wherein the timing correction means comprises a pipeline of registers, each of which determines time offset for a particular physical effect and then applies the obtained time offsets to the data to compensate for this effect as a function of the current data and previous data.

6. The apparatus according to claim 5, wherein the number of pipe stages of registers is twice the number of symbols that are stored in a transmission medium, to compensate signal reflections in transmission lines.

7. The apparatus according to claim 1, wherein the storage means comprises a set of look-up tables, one look-up table being allocated per signal wire.

8. The apparatus according to claim 1, wherein the storage means comprises a set of look-up tables, one look-up table being allocated across adjacent signal wires.

9. The apparatus according to claim 1, wherein the storage means comprises a set of look-up tables, one look-up table being allocated across all signal wires.

10. The apparatus according to claim 1, wherein each transmitter'"'"'s register is further connected to a vernier delay, the value of delay being determined as a function of delay values in a respective look-up-table allocated to that signal wire.

11. The apparatus according to claim 1, wherein the time between the timing position of a signal transition between two logical levels, on one side, and the reference clock edge, on the other side, is determined in terms of the actual delay of logic elements.

12. A method for automatic skew calibration of a transmission apparatus for high-speed transmission of digital data, comprising a transmitter and a receiver, the method comprising the steps of:

calibrating registers of the receiver in relation to a reference clock edge;

calibrating propagation delays of registers of the transmitter, using the calibrated registers of the receiver,

wherein the calibration is performed by

measuring time offsets between different signals that form a communication channel, for a plurality of frequencies, or for a plurality of data patterns, and

applying the measured time offsets to compensate for said inter-signal skew by performing relative alignment of the measured offsets to a main clock edge.

13. The method as claimed in claim 12, wherein the time offsets are determined for each different physical effect and then the obtained time offsets are applied to the data to compensate for this particular effect as a function of the current data and previous data.

14. The method according to claim 12, wherein the obtained time offsets are stored in a plurality of look-up tables.

15. The method as claimed in claim 12, wherein the time offset is determined as a function of delay values in each of the look-up-table that relates to that signal wire.

16. The method as claimed in claim 12, wherein the time offset is determined by summation of delay values in each of the look-up-table that relates to that signal wire.

17. The method as claimed in claim 12, wherein a data pattern mask is applied for one edge in a plurality of edges in a pattern.

18. The method as claimed in claim 12, wherein the time between the timing position of a signal transition between two logical levels, on one side, and the reference clock edge, on the other side, is determined in terms of the actual delay of logic elements.

19. The method as claimed in claim 12, wherein the time offset is calculated based on the only one data pattern stored, the time offsets for other data patterns being calculated on the basis of said time offset and correction factors for other data patterns.

20. The method as claimed in claim 19, wherein the correction factors are stored per each symbol.