Data rate supply proportional to the ratio of different printhead lengths

• US 7,278,697 B2
• Filed: 11/14/2005
• Issued: 10/09/2007
• Est. Priority Date: 12/02/2002
• Status: Expired due to Fees

• Current Assignee: Memjet Technology Ltd. (Memjet Limited)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Plunkett, Richard Thomas
• Primary Examiner(s): Luu; Matthew
• Assistant Examiner(s): FIDLER, SHELBY LEE
• Application Number:
  US11/272,491
• Publication Number:
  US 20060071981A1
• Time in Patent Office: 694 Days
• Field of Search: None
• US Class Current: 347/5
• CPC Class Codes: B41J 2/04505 aiming at correcting alignment
• CPC Class Codes: B41J 2/04508 aiming at correcting other parameters
• CPC Class Codes: B41J 2/0451 for detecting failure, e.g. clogging, malfunctioning actuator
• CPC Class Codes: B41J 2/04528 aiming at warming up the head
• CPC Class Codes: B41J 2/04541 Specific driving circuit
• CPC Class Codes: B41J 2/04543 Block driving
• CPC Class Codes: B41J 2/04563 detecting head temperature; Ink temperature
• CPC Class Codes: B41J 2/04573 Timing; Delays
• CPC Class Codes: B41J 2/04586 controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
• CPC Class Codes: B41J 2202/20 Modules
• CPC Class Codes: G06F 21/554 involving event detection and direct action
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04N 1/405 Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
• CPC Class Codes: Y10S 707/99933 : Query processing, i.e. searching
• CPC Class Codes: Y10S 707/99939 : Privileged access
• CPC Class Codes: Y10T 29/49401 : Fluid pattern dispersing device making, e.g., ink jet

Abstract

A printer controller configured to generate dot data for supply to a printhead which includes at least a first printhead integrated circuit and a second printhead integrated circuit positioned adjacent each other either side of a join region, the printer controller configured to transfer dot data to each of the first printhead integrated circuit and the second printhead integrated circuit at a rate proportional to the relative lengths of the first printhead integrated circuit and the second printhead integrated circuit.

Claims

1. A printer controller configured to generate dot data for supply to a pagewidth printhead which includes at least a first printhead integrated circuit and a second printhead integrated circuit arranged adjacent each other either side of a join region, the first and second printhead integrated circuits having different lengths which aggregate in said adjacent arrangement so that the first and second printhead integrated circuits extend across said pagewidth, the printer controller configured to transfer dot data to each of the first and second printhead integrated circuits at a rate proportional to the relative lengths of the first and second printhead integrated circuits so that the dot data is transferred to each of the first and second printhead intergated circuits in equal time.

2. The printer controller as claimed in claim 1, wherein the printer controller includes a printhead interface in communication with a line loader unit.

3. The printer controller as claimed in claim 2, wherein the printhead interface transfers the dot data to the first printhead integrated circuit and the second printhead integrated circuit at a pre-programmed rate.

4. The printer controller as claimed in claim 1, wherein the dot data transfer rate is controlled by at least one register.

5. The printer controller as claimed in claim 4, wherein there is provided one register per printhead integrated circuit.

6. The printer controller as claimed in claim 1, wherein the dot data transfer rate can be varied between 0 to 100% of maximum capacity.

7. The printer controller as claimed in claim 2, wherein the printhead interface accepts two streams of dot data from the line loader unit.

8. The printer controller as claimed in claim 7, wherein the line loader unit includes two dot data generator units.

9. The printer controller as claimed in claim 2, wherein the line loader unit compensates for any vertical misalignment between the first printhead integrated circuit and the second printhead integrated circuit.

10. The printer controller as claimed in claim 2, wherein the line loader unit generates dot data at a rate of at least 12 bits per cycle, where a cycle is the system clock period.

11. The printer controller as claimed in claim 1, wherein the dot data is transferred to either the first printhead integrated circuit or the second printhead integrated circuit from a memory under the control of the printhead controller.

12. The printer controller as claimed in claim 1, configured to manipulate the supply of dot data to each of the printhead integrated circuits such that usage of a memory bandwidth is substantially constant during a printhead loading cycle.