Thin film transistor array substrate and method of fabricating the same

• US 7,279,370 B2
• Filed: 10/06/2004
• Issued: 10/09/2007
• Est. Priority Date: 10/11/2003
• Status: Expired

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kim, Hong Sik, Lim, Byoung Ho, Cho, Heung Lyul, Seo, Hyun Sik
• Primary Examiner(s): Loke; Steven
• Assistant Examiner(s): Nguyen; Dao H.
• Application Number:
  US10/958,260
• Publication Number:
  US 20050077516A1
• Time in Patent Office: 1,098 Days
• Field of Search: 438/30, 438/149, 438/155, 438/158, 349/43
• US Class Current: 438/155
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors

Abstract

A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.

Claims

1. A method of fabricating a thin film transistor array substrate, comprising:

forming a gate pattern on a substrate, the gate pattern including a gate electrode of a thin film transistor, a gate line connected to the gate electrode, and a lower gate pad electrode connected to the gate line;

forming a gate insulating film on the substrate having the gate pattern;

forming a source/drain pattern including a source electrode and a drain electrode of the thin film transistor, a data line connected to the source electrode and a lower data pad electrode connected to the data line, and a semiconductor pattern formed beneath the source/drain pattern there along; and

forming a transparent electrode pattern and a passivation film pattern stacked on remaining areas except for areas at which the transparent electrode pattern is formed,

wherein the transparent electrode pattern includes a pixel electrode directly contacting both the drain electrode and the semiconductor pattern and formed on the gate insulating film, and the pixel electrode directly contacts an upper gate pad electrode and the lower gate pad electrode along sides of the upper and lower gate pad electrodes, and the pixel electrode directly contacts an upper data pad electrode and the lower data pad electrode along sides of the upper and lower data pad electrodes.

2. The method according to claim 1, wherein the step of forming the transparent electrode pattern and the passivation film pattern includes:

forming a passivation film on the substrate having the source/drain pattern formed thereon;

forming a photo-resist pattern having a step height on the passivation film;

patterning the gate insulating film and the passivation film by using the photo-resist pattern to expose the lower gate pad electrode;

ashing the photo-resist pattern to expose the passivation film corresponding to the pixel electrode and the upper data pad electrode;

etching the exposed passivation film by using the ashed photo-resist pattern;

depositing a transparent material on the substrate having a residual photo-resist pattern; and

removing the residual photo-resist pattern and the transparent electrode material on the residual photo-resist pattern to form a transparent electrode pattern.

3. The method according to claim 1, further comprising a storage capacitor including the gate line and a storage electrode overlapping the gate line with the gate insulating pattern and the semiconductor pattern positioned therebetween.

4. The method according to claim 3, wherein the step of forming the passivation film pattern includes partially exposing the drain electrode and the storage electrode to be connected to the pixel electrode.

5. A method of fabricating a thin film transistor substrate, comprising:

preparing a transparent substrate;

depositing a first metal film on the substrate and then forming a gate line, a gate electrode and a gate pad through a first mask process;

sequentially stacking a first insulating film, an amorphous silicon layer, an n⁺ amorphous silicon layer and a second metal film on an entire surface of the substrate having the gate electrode and the gate line, and forming a data line vertically crossing the gate line and defining a pixel region together with the gate line, a semiconductor layer having an active layer and an ohmic contact layer, a source/drain electrode, and a data pad through a second mask process; and

forming a second insulating film on an entire surface of the substrate having the data line and the source/drain electrode, exposing the first insulating film of the pixel region, the gate pad and the data pad through a third mask process, depositing a transparent conductive film on an upper portion of the first insulating film, the gate pad and the data pad, to thereby form a pixel electrode directly contacting both the drain electrode and the ohmic contact layer, directly contacting a gate connection terminal and the gate pad along sides of the gate connection terminal and gate pad, and directly contacting a data connection terminal and the data pad along sides of the data connection terminal and data pad.

6. The method according to claim 5, wherein the second mask process includes:

applying a photo-resist film on the second metal film;

irradiating light to the photo-resist film through a mask having a partial exposure region partially transmitting the light and a transmission region entirely transmitting the light and a shielding region shielding the light;

developing the photo-resist film to which the light is irradiated through the mask to form a photo-resist pattern on the second metal film, wherein the photo-resist pattern includes a first photo-resist pattern having a first thickness formed at the partial exposure region and a second photo-resist pattern having a second thickness formed at the transmission region;

etching the amorphous silicon layer, the n+ amorphous silicon layer and the second metal film by using the first and the second photo-resist patterns as masks to form the data line, the active layer, the ohmic contact layer and the data pad;

removing the first photo-resist pattern to expose a middle region of the second metal film formed on the ohmic contact layer; and

removing portions of the second metal film and the ohmic contact layer by using the second photo-resist pattern as a mask to form the source/drain electrode.

7. The method according to claim 6, wherein a molybdenum silicide (MoSi) film is formed at the partial exposure region of the mask, and a chromium (Cr) film is formed at the shielding region.

8. The method according to claim 6, wherein the partial exposure region of the mask includes a slit.

9. The method according to claim 6, further comprising forming a storage electrode at the time of the formation of the source/drain electrodes, wherein the storage electrode overlaps the gate line to form a storage capacitor.

10. The method according to claim 5, wherein the first thickness of the first photo-resist pattern is less than the second thickness of the second photo-resist pattern.

11. The method according to claim 5, wherein the third mask process includes:

applying a photo-resist film on the second metal film;

irradiating light to the photo-resist film through a mask having a partial exposure region partially transmitting the light, a transmission region entirely transmitting the light, and a shielding region shielding the light;

developing the photo-resist film to which light is irradiated through the mask to form a photo-resist pattern on the second metal film, the photo-resist pattern including a first photo-resist pattern having a first thickness formed at the partial exposure region and a second photo-resist pattern having a second thickness formed at the transmission region;

etching the first and the second insulating films by using the first and the second photo-resist patterns as masks to form a first contact hole exposing the gate pad and a second contact hole exposing a lateral surface of the data pad;

removing the first photo-resist pattern;

removing the second insulating film of the pixel region by using the second photo-resist pattern as a mask to expose the first insulating film;

depositing the transparent conductive film along an entire surface of the substrate having the second photo-resist pattern, and

removing the second photo-resist pattern and the transparent conductive film formed on the second photo-resist pattern to form the pixel electrode, the gate connection terminal connected via the first contact hole to the gate pad, and the data connection terminal connected via the second contact hole to the data pad.

12. The method according to claim 5, further comprising forming a repair pattern at a lower portion of the data line.

13. The method according to claim 12, wherein the repair pattern is formed along with the gate line during the first mask process.

14. The method according to claim 5, wherein the transparent conductive film is made of one of indium-tin oxide (ITO) and indium-zinc-oxide (IZO).

15. The method according to claim 5, wherein the pixel electrode is formed to be overlapped with the gate line.

16. A method of fabricating a thin film transistor array substrate, comprising:

preparing a transparent substrate;

forming a gate line, a gate electrode, and a gate pad on the substrate;

forming a gate insulating film along an entire surface of the substrate having the gate electrode and the gate pad;

forming a data line to vertically cross the gate line and defining a pixel region together with the gate line, a semiconductor layer having an active layer and an ohmic contact layer, a source/drain electrode, and a data pad, the data pad includes portions of the semiconductor layer and the ohmic layer;

exposing the gate insulating film formed at each pixel region;

forming a passivation film along an entire surface of the substrate having the data line and the source/drain electrode;

applying a photo-resist film to an upper portion of the passivation film;

forming a photo-resist pattern on the passivation film by using a mask;

forming a contact hole exposing each of the gate pad and the data pad by using the photo-resist pattern as a mask for etching, and exposing the gate insulating film of the pixel region;

depositing a transparent conductive film along an entire surface of the substrate having the photo-resist pattern, the gate insulating film of the pixel region and the contact hole;

removing the photo-resist pattern and the transparent conductive film formed on the photo-resist pattern to form a pixel electrode directly contacting the gate insulating film of the pixel region parallel to the entire surface of the substrate, and forming a gate connection terminal and a data connection terminal respectively connected via the contact hole to the gate pad and the data pad, the data connection terminal contacting the side regions of the portions of the semiconductor layer and the ohmic contact layer of the data pad.

17. The method according to claim 16, wherein the pixel electrode is formed to be overlapped with the gate line.

18. The method according to claim 16, further comprising forming a storage electrode overlapping the gate line when the source/drain electrodes are formed.

19. The method according to claim 16, wherein the step of forming the data line, the semiconductor pattern having the active layer and the ohmic contact layer, the source/drain electrodes, and the data pad includes:

sequentially stacking an amorphous silicon layer, an n+ amorphous silicon layer, and a metal film on the gate insulating film;

applying a photo-resist film on the metal film;

irradiating light to the photo-resist film through a mask, the mask having a partial exposure region partially transmitting the light and a transmission region entirely transmitting the light and a shielding region shielding the light;

developing the photo-resist film to which light is irradiated through the mask to form a photo-resist pattern on the metal film, the photo-resist pattern including a first photo-resist pattern having a first thickness formed at the partial exposure region and a second photo-resist pattern having a second thickness formed at the transmission region;

etching the amorphous silicon layer, the n+ amorphous silicon layer, and the metal film by using the first and the second photo-resist patterns as a mask to form the data line, the active layer, the ohmic contact layer, and the data pad;

removing the first photo-resist pattern to expose a middle region of the metal film formed on the ohmic contact layer; and

removing a part of the metal film and the ohmic contact layer by using the second photo-resist pattern as a mask to form the source/drain electrodes.

20. The method according to claim 19, wherein the first thickness of the first photo-resist pattern is less than the second thickness of the second photo-resist pattern.

21. The method according to claim 16, wherein forming the photo-resist pattern on the passivation film includes:

applying a photo-resist film on the passivation film;

irradiating light to the photo-resist film through the mask, the mask having a partial exposure region partially transmitting the light and a transmission region entirely transmitting the light and a shielding region shielding the light;

developing the photo-resist film to which light is irradiated through the mask to form a photo-resist pattern on the passivation film, the photo-resist pattern including a first photo-resist pattern having a first thickness formed at the partial exposure region and a second photo-resist pattern having a second thickness less than the first thickness formed at the transmission region.

22. The method according to claim 21, wherein a portion of the gate insulating film and a portion of the passivation film are etched by using the first and the second photo-resist patterns as masks to form contact holes for exposing the gate pad and the data pad, removing the first photo-resist pattern, and removing the passivation film of the pixel region by using the second photo-resist pattern as a mask to expose the gate insulating film of the pixel region.

23. The method according to claim 22, wherein the first photo-resist pattern is removed through an ashing process.

24. The method according to claim 21, wherein the photo-resist pattern includes the second photo-resist pattern.